Incremental-step-pulse programming (ISPP) is a key enabler for achieving tight V T distribution for MLC NAND Flash. The ISPP characteristics for BE-SONOS NAND Flash are studied extensively in this ...work. Experimentally we find that the ISPP slope is very close to 1 for BE-SONOS capacitors for a wide range of EOT and O1 variations. A theoretical model is developed to prove that ISPP slope~1 is a universal property for any charge-trapping devices, assuming charges are fully captured. However, when the device is integrated in various STI geometries, the ISPP slope is often degraded. This is due to the STI edge effect. Non-uniform injection happens along the channel width and degrades the programming efficiency at higher V T levels. The degradation of trans-conductance (g m ) and subthreshold slope (S.S) during programming validates the STI edge effect. We find that through process modifications for the STI edge, the ISPP slope can be improved.
In-process charging effect is found to deteriorate the initial Vt distribution of 3D NAND Flash. In this work, we propose a novel antenna protection circuit using a capacitive coupled floating gate ...(CCFG) CMOS circuit that can be applied to the word line (WL), string select (SSL) and ground select transistor (GSL) decoders. Experimental results show a very low turn-on voltage (<; +/-2V) for discharging, providing ideal protection for the memory devices. With this novel technique, our fully-integrated 3D NAND Flash device shows excellent initial Vt distribution free from the charging effect. Furthermore, the impact of SSL Vt distribution on the minimal Vdd bias is studied. With optimal SSL Vt distribution, it is demonstrated that 3D VG NAND Flash can support Vdd as low as 1.6V with successful programming window.
We propose optimal design methods of 3D NAND Flash to achieve high-density, high-bandwidth and low-power nvCIM. By suitably engineering the device, we can produce ultra-low ON current of 2nA (mean) ...at saturated region instead of subthreshold region, while the OFF leakage current is much below 1pA. Such low Ion and large ON/OFF ratio provide large bandwidth to parallelly sum more than 10'000 cells together to offer high efficiency for DNN computing. The three-dimensional summation in 3D NAND also allows effective multi-bit resolution of weight without resorting to complex analog memory design. For the first time we witnessed the power of "central limit theory" in 3D NAND nvCIM, where the large number of summation averages out the noise and provides high accuracy of MAC. The effect of non-ideal cell variations, noises and shifts are studied systematically. Through adequate calibration techniques the 3D NAND nvCIM can provide accuracy close to the software limitation, with reasonable tolerance to various device errors. The 3D NAND nvCIM is promising to be an energy-efficient (TOPS/W~40) edge computing solution for large neural networks (>100Mb weight).
Multi-level cell (MLC) programming is of crucial importance to make a cost competitive NAND Flash product. In conventional 2D floating gate NAND Flash, the interference and disturb become very severe ...as technology scales, and many methods have been adopted to alleviate the interferences. In 3D NAND, the pitch is generally larger and the charge-trapping device naturally has smaller interference. However, disturb and interference now come from three dimensions and new understanding of device properties must be gained in order to achieve MLC operation.
Despite vertical stacking, the lateral scaling of 3D NAND Flash is critically important because otherwise >;16 stacking layers are needed to be cost competitive to 20nm 2D NAND. In this work, we ...propose a 3D vertical gate (VG) NAND using a self-aligned independently controlled double gate (IDG) string select transistor (SSL) decoding method. The IDG SSL provides excellent program inhibit and read selection without any penalty of cell size increase, making our 3D VG NAND cell as scalable as conventional 2D NAND. We present the world's first <; 50nm (37.5nm) half-pitch 3D NAND. The BL decoding and page operation methods are illustrated in detail. This highly pitch scalable VG with IDG SSL approach provides a very cost competitive 3D NAND.
A novel PN diode decoding method for 3D NAND Flash is proposed. The PN diodes are fabricated self-aligned at the source side of the Vertical Gate (VG) 3D NAND architecture. Contrary to the previous ...3D NAND approaches, there is no need to fabricate plural string select (SSL) transistors inside the array, thus enabling a highly symmetrical and scalable cell structure. A novel three-step programming pulse waveform is integrated to implement the program-inhibit method, capitalizing on that the PN diodes can prevent leakage of the self-boosted channel potential. A large program-disturb-free window >;5V is demonstrated.
Computing-In-Memory (CIM) using Flash memory is a potential solution to support a heavy-weight DNN inference accelerator for edge computing applications. Flash memory provides the best high-density ...and low-cost non-volatile memory solution to store the weights, while CIM functions of Flash memory can compute AI neural network calculations inside the memory chip. Our analysis indicates that Flash CIM can save data movements by ~85% as compared with the conventional Von-Neumann architecture. In this work, we propose a detail device and design co-optimizations to realize Flash CIM, using a novel vertical split-gate Flash device. Our device supports low-voltage (<1V) read at WL's and BL's, tight and tunable cell current (Icell) ranging from 150nA to 1.5uA, extremely large Icell ON/OFF ratio ~ 7 orders, small RTN noise and negligible read disturb to provide a high-performance and highly-reliable CIM solution.
We substantially enhanced the 3D DRAM GCT 1 device by incorporating the principles of cross-bar array selection. The GCT device provides ideal self-rectifying I BL -V BL curves with super steep slope ...at forward break-over voltage of 1.7V, large ON/OFF ratio >1E6 at read, and ultra-low leakage current <1pAper cell at reverse read. It therefore enables efficient cross-bar selection for a large-density array due to its low background leakage. The "Program" operation involves applying a high BL bias (>=1.9V) over the threshold, while "Read" operation entails applying a low BL bias (<=1.5V) below threshold. The GCT device latches up the gate-controlled "PNPN" diode after program, and exhibits no read disturb during continuous read operation lasting 10,000 sec. The multi-gate (three) WL biases remain fixed during read/program operations to facilitate a simple design. The WL bias is only changed during sector erase. This cross-bar selection technique enables vertical-BL 3D DRAM for improved sensing while allowing for practical processing with loosely spaced staircase contacts on the source line. The WL's are shared vertically and laterally, enabling aggressive X/Z pitch scaling without facing the challenges of vertical-gate 3D DRAM. It is estimated that this 3D GCT DRAM is suitable for dimension scaling below 10nm. We have verified the feasibility of array selections for read, program, and erase in both selected and unselected sectors. The GCT device shows promising potential to realize simultaneous pitch scaling and high-layer stacking for 3D DRAM. It demonstrates high endurance >1E10 (measured, and projected to be infinite), and holds good potential to realize DRAM-based computing in memory (CIM).
A novel P-channel nitride trapping nonvolatile memory device is studied. The device uses a P/sup +/-poly gate to reduce gate injection during channel erase, and a relatively thick tunnel oxide (>5 ...nm) to prevent charge loss. The programming is carried out by low-power band-to-band tunneling induced hot-electron (BTBTHE) injection. For the erase, self-convergent channel erase is used to expel the electrons out of nitride. Experimental results show that this p-channel device is immune to read disturb due to the large potential barrier for hole tunneling. Excellent P/E cycling endurance and retention properties are demonstrated. This p-channel device shows potential for high-density NAND-type array application with high-programming throughput (>10 Mb/sec).
We demonstrate a novel p-channel 3D stackable NAND Flash that uses completely new programming and erasing methods. The p-channel 3D NAND avoids the disadvantage of GIDL induced hole erase of floating ...body n-channel NAND, giving a highly efficient -FN hole erasing and negligible disturb on the SSL and GSL devices. The p-channel NAND structure enables a novel -FN erase selection method, providing a unique feature of bit alterable erase that facilitates small-unit random code overwrite without block erase. Furthermore, the band-to-band tunneling induced hot-electron programming method provides lower operation voltage and is good for peripheral CMOS scaling. The device concept is demonstrated on a 37.5nm half-pitch 3D vertical gate (VG) junction-free NAND architecture.
