In this work, we report two performance enhancement schemes for single-gate vertical-channel (SGVC) 3-D NAND Flash. The first one features a programming (PGM) waveform where the bias of the dummy ...wordline (DWL) is raised in a two-step manner so that the resultant disturbance that the DWL and edge WL suffer is appreciably alleviated. The second scheme takes advantage of a unique behavior termed "self-boosting-enhanced-PGM" mechanism in the pair- bitline PGM method to deal with the slow PGM bits and achieve a much lower bit error rate as a consequence. By using these two approaches, the bit error rate after multilevel cell (MLC) operation can be substantially improved by 82%.
The 3-D stacking of multiple layers of NAND using thin-film transistor (TFT) devices is widely accepted as the next step in continuing NAND Flash scaling. Low mobility and reliability problems are ...two well-known concerns regarding TFT devices. However, another important implication of using TFT devices is that the Vt variation induced by randomly distributed grain boundaries degrades the array performance. In this paper, an extensive TCAD simulation was conducted to systematically investigate how grain boundary generated traps affect NAND Flash devices. Minimizing the density of grain boundary traps is crucial for array performance. In addition, optimal gate control ability reduces the impact of grain boundaries. Thus, using double gate architecture in vertical gate 3-D NAND is favorable. Furthermore, when pitch is scaled in the future, device exhibiting smaller channel thickness should be used to increase the gate control.
For the first time, we experimentally demonstrate an FET with a polycrystalline silicon (poly-Si) device featuring supersteep subthreshold slope (SS) around 20 mV/decade at room temperature. This ...novel dual-channel device is a three-wordline(WL) transistor fabricated in a poly-Si channel, with p + source and n + drain. The outer two WLs serve as the pass gates that control the virtual junction of the center WL device (main gate). Whether n-channel or p-channel characteristics are achieved depend on the bias polarity applied to the pass gates. Both read modes exhibit supersteep SS behavior for the center main gate. Theoretical analysis suggests that this three-WL FET device creates a gate-controlled thyristor mode, where a positive feedback current is induced when the center main gate voltage is above the onset value to induce the turnedon thyristor. Different from the usual tunneling FET (with reverse-biased junction bias), the p + /n + junction is forward biased, and thus, the read current can approach 10 μA even for a narrow-width (~32 nm) poly-Si thin-film transistor, amounting to 0.3-mA/μm drive current. This device displays no hysteresis between forward and reverse voltage sweeping, and the steep SS has weak temperature/size dependence.
3D vertical-gate (3DVG) NAND flash is a promising candidate for next-generation high-density nonvolatile memory. Cross-layer process variation renders 3DVG NAND susceptible to decreased speeds, ...yield, and reliability. This can be attributed to (a) cross-layer mismatch in bitline capacitance (CBL), (b) the need for long program cycles, and (c) sensing-margin (SM) loss induced by the effects of background-pattern-dependency (BPD). This study proposes three circuit-level techniques to overcome these issues by employing the following: (1) distributed NAND-string scramble (DNSS), (2) layer-aware program-verify-and-read (LA-PV-R), and (3) a layer-aware-bitline-precharge (LA-BP) scheme. For an 8-layer 3DVG with 200 mV cross-layer mismatch in cell threshold voltage ( V THC), DNSS reduces the cross-layer C BL-mismatch by 41%, LA-PV-R using various program-threshold-voltages ( V THP) for each layer enables a 25% reduction in the number of program cycles, and LA-BP succeeds in reducing BPD-induced SM loss by 56%. A 2-layer 3DVG NAND testchip and 8-layer testkey were fabricated to evaluate the proposed methods. The LA-PV-R and LA-BP have achieved a 0.75 V difference in V THP between layer-0 and layer-1 with a 0.4V difference in BL clamping bias voltages and the LA-BP scheme has achieved a 44% reduction in BPD-induced SM loss. The three proposed schemes incur an area penalty of less than 0.1% in a Gb-scale 3DVG NAND device.
A novel confined nitride (SiN) charge trapping 3-D NAND flash with excellent postcycling retention performances was demonstrated. Using a uniform sidewall lateral recess in the 3-D stack followed by ...a SiN pull-back process to isolate the SiN trapping layer in a self-aligned way is critical to facilitate this structure. Lower erase saturation <; -4 V was shown in the confined SiN cell because of discrete SiN along the Z-direction. Therefore, this structure is in favor of the larger memory window (>10 V) design. Random telegraph noise (RTN) characteristics are comparable to the traditional 3-D NAND device with <; 0.1-V variation. Excellent single-level cell (SLC) retention with only ~600-mV charge loss after 125 °C one-week high-temperature baking for a post-1K-cycled device was obtained. It is far superior to the control sample without a confined SiN structure. Arrhenius analysis at various baking temperatures shows that the retention may pass >100 years at 60 °C and even longer at room temperature. Moreover, superior post-1K-cycled multilevel cell (MLC) retention was also illustrated, which even sustains 150 °C and one-week baking. Therefore, the device has the potential to meet the low-cost long-retention archive memory applications.
A novel double-density hemi-cylindrical (HC) structure 3-D NAND Flash architecture was demonstrated (Lue et al. , 2019). HC 3-D NAND squeezes the gate-all-around (GAA) hole in one direction, followed ...by a slit cut to split the GAA device to produce twin cells, thus creating >2.5 times of memory density than standard GAA 3-D NAND at the same stacking layer. It is demonstrated that the extremely scaled HC 3-D NAND shows excellent 100k endurance and large memory window >10 V. Contrary to the standard GAA 3-D NAND, HC device has special edge effect issue. For taller HC device, a "wake-up" effect (Du et al. , 2020) by an initial strong -FN erasing can introduce gate injected electrons that electrically suppress the parasitic edge and in turn "wake-up" the device to produce a larger programming window. TCAD simulation clearly shows asymmetrical <inline-formula> <tex-math notation="LaTeX">{E} </tex-math></inline-formula>-field distribution from bottom oxide field to top oxide field at Region I (HC tip) and Region II (bottom edge). Through the comprehensive investigation of HC device "wake-up" effect and strong -FN for initial reset, the variation of cell to cell operation window is minimized and aligned to extremely scaled "hero" HC devices that enjoy field enhancement effect (Hsu et al. , 2007). Our results suggest a promising path of 3-D NAND device toward aggressive dimension scaling and large memory window.
Lower saturation current flowing through the same cell twice is a major drawback of vertical stack array transistor architecture. A loading effect further reduces the saturation current and causes ...higher threshold voltage. A simple word line cut process not only doubles the bit density to reduce the bit cost, but also reduces the loading effect. This letter used an assisted gate can to further enhance the saturation current with acceptable cell characteristics. Furthermore, the major parameters that influence the performance of the vertical stack array transistor architecture were studied extensively. An ultra-high density three-dimensional NAND flash architecture can be used in the future NAND flash industry.
Using a recently developed gate-sensing and channel- sensing (GSCS) transient analysis method, we have studied the detailed charge-trapping behavior for SONOS-type devices. By adding gate sensing to ...the conventional channel sensing, the two variables (total charge Q tot and mean vertical location x circ) can be solved simultaneously. By using this powerful new tool on several SONOS-type structures, we have studied the charge centroid as well as the capture efficiency of various SONOS devices. Our results clearly prove that electrons are mainly distributed inside the bulk nitride instead of the interfaces between oxide and nitride. For the first time, we show that nitride 7 nm or thicker can essentially capture electrons with 100% efficiency up to a density of Q tot ~10 13 cm -2 . Structures without top blocking oxide suffer from hole back tunneling and show apparent low electron capture efficiency, which led to confusion in the past. Moreover, multilayer stacks of nitride-trapping layers do not provide more efficient interfacial traps.
The physical model for field enhancement (FE) and the edge effects of body-tied FinFET charge-trapping NAND Flash devices are extensively studied in this paper. First, analytical equations are ...derived to provide insight to the FE effect for FinFET devices, and these analytical results are validated by 3-D TCAD simulation and experimental verification. Next, complicated programming and erasing characteristics and transconductance and subthreshold slope ( gm / SS ) behaviors are completely explained by the nonuniform injection behavior along various corner edges in FinFET. FE allows high program and erase speed and larger memory window. On the other hand, the edge effect complicates the device DC I - V , as well as programming and erasing characteristics, and these must be taken into account in memory circuit design.
An AND-type stackable 3D NVM architecture is proposed to provide an ultra-high density AI computing memory with low power. The advantages are: (1) All memory transistors in the 3D array are connected ...in parallel, thus enable the sum-of-product operation. (2) The 3D NAND like architecture is possible to stack to > 64 layers, thus provides ultra-high density (>128Gb) AI memory. (3) Many bit lines (>1KB) can operate in parallel for high bandwidth. (4) Uses low-power +/− FN programming/erasing which allows high parallelism, and is bit-alterable thus is ideal for training or transfer learning. (5) Excellent linearity of output current with respect to bitline bias, thus enabling ideal analog computation. (6) Adequate sensing current of the summed product thus permits fast access read for inference device. The proposed memory architecture can achieve TOPS/W>10, which is 10X greater than the conventional von Neumann architecture.
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