Developed within RD51 Collaboration for the Development of Micro-Pattern Gas Detectors Technologies, the Scalable Readout System (SRS) is intended as a general purpose multi-channel readout solution ...for a wide range of detector types and detector complexities. The scalable architecture, achieved using multi-Gbps point-to-point links with no buses involved, allows the user to tailor the system size to his needs. The modular topology enables the integration of different front-end ASICs, giving the user the possibility to use the most appropriate front-end for his purpose or to build a heterogeneous experimental apparatus which integrates different front-ends into the same DAQ system. Current applications include LHC upgrade activities, geophysics or homeland security applications as well as detector R&D. The system architecture, development and running experience will be presented, together with future prospects, ATCA implementation options and application possibilities.
The Read-Out Controller (ROC) ASIC is an on-detector custom real-time data packet processor for the upgraded New Small Wheel (NSW) Trigger and Data Acquisition (TDAQ) system of the ATLAS Experiment ...at CERN, Geneva. The ROC is a highly-configurable data concentrator that allows the optimization of bandwidth utilization, reduces the required number of data links, minimizes data loss, implements congestion and flow control mechanisms, allows data filtering, supplies phase adjustable clock signals and offers relatively larger buffer spaces for the readout system. The paper details the designed, implemented and deployed FPGA-based test setup for the quality-control of the ROC packet processing logic. The FPGA-based test setup emulates the ROC context using firmware-based input data streams emulators and output data analyzers which are controlled and monitored by a soft-core Xilinx MicroBlaze microprocessor instantiated on the same FPGA. The ROC chip is accommodated on a custom PCB which assures the power supply and the interface to the FPGA. A mathematical model of the ROC performance as a function of its configuration and input data throughput is proposed. The ROC digital design was successfully validated and its performance assessed, confirming the theoretical model. The design coverage, test procedure and partial mass-testing results are presented and analyzed.
Abstract RDMA communication is an efficient choice for many applications, such as data acquisition systems, data center networking and any other networking application, where high bandwidth and low ...latency are necessary. RDMA can be implemented using a large array of options, which need to be tailored to the needed use case, in order to get optimal results. Aspects such as the effects of using multiple simultaneous connections, using various transport functions such as RDMA Write and RDMA Send and communication models such as sending individual bursts or continuous streams of data will be investigated for implementing RDMA on FPGA devices.
Following the Large Hadron Collider upgrade phase from 2019-2020, the innermost station of the ATLAS Muon Spectrometer is being replaced with a newly enhanced detector system. The new associated ...electronic system will provide improved precision tracking and triggering for the expected high background rates. In this system, the Read-Out Controller (ROC) ASIC is an essential on-detector custom real-time data packet processor. It buffers, filters and aggregates the digitized data from up to 512 upgraded muon detectors and distributes phase-adjustable clock signals and control commands. It is fundamental to verify the robustness of ROC and its data integrity despite the neutron dose at which it is expected to be exposed. This paper briefly describes the ROC architecture, data formats, die layout and implemented techniques for the mitigation of radiation effects. The ROC test apparatus and irradiation testing are thoroughly presented, giving emphasis to the immunity to the produced single event upsets (SEUs) and the effects of data corruption inside its SRAM. Two ROC samples were subjected to neutron beams with 20, 22 and 24 MeV energies, for over 39 hours, at an average flux of 9.5×105 nċcm−2ċs−1, totaling a dose equivalent to 8 months of operation in LHC at L=1034 cm−2ċs−1. Flip-Flops were affected by 69 SEUs yet the ROC operation was not disturbed by this, but data corruption in memories occurred with a considerable rate. Statistics of the resulting errors are presented.
Abstract
The FELIX system is used to interface the front-end electronics and the commodity hardware in the server farm of the ATLAS experiment. FELIX is using RDMA through RoCE to transmit data from ...its host servers to the Software Readout Driver using off-the-shelf networking equipment. In the current version of FELIX, RDMA communication is implemented using software on both ends of the links. Improvements of the data throughput as part of the High Luminosity LHC upgrade, by implementing RDMA support in the front-end FELIX FPGA, have been tested. A version of FELIX that uses the FPGA implementation of RDMA is being proposed and demonstrated.
Abstract
The FELIX system is used as an interface between front-end electronics and commodity hardware in the server farm. FELIX is using RDMA through RoCE to transmit data from its host servers to ...the software readout driver using off-the-shelf networking equipment. RDMA communication is implemented using software on both end of the links. Exploring opportunities to improve data throughput as part of the high luminosity LHC upgrade, an implementation for RDMA support in the front-end FELIX FPGA is being developed. We present a proof-of-concept RDMA FPGA implementation, which will help inform the design of the FELIX platform for high luminosity LHC.
Implementation of the VMM ASIC in the Scalable Readout System Lupberger, M.; Bartels, L.; Brunbauer, F.M. ...
Nuclear instruments & methods in physics research. Section A, Accelerators, spectrometers, detectors and associated equipment,
09/2018, Letnik:
903
Journal Article
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Odprti dostop
The Scalable Readout System (SRS) developed by the RD51 collaboration is a versatile and multi-purpose approach, which is used with different front-end chips to transfer data from detectors to ...computers. Targeting mainly micro-pattern gaseous detectors, the system is also applicable for silicon strip or pad detectors. The most frequently used front-end chip today is the APV25, originally developed for the CMS pixel detector. In the scope of the ATLAS New Small Wheel upgrade, a new front-end chip, the VMM, is developed, which has significantly improved specifications compared to the APV25.
We report on the implementation of the VMM in the Scalable Readout System carried out by the RD51 collaboration in the framework of a detector project related to the European Spallation Source ERIC. Due to the hierarchical design of the Scalable Readout System, only specific parts of the readout chain need to be adapted or designed, which is the carrier board for the front-end chip, an adapter card that connects to the common hardware of the system and the firmware for a field programmable gate array. In addition, we have developed dedicated software for slow control, data acquisition and online monitoring. The readout system has been tested in the laboratory and in particle beams and we present results which proof the functioning of the system, even though it is still in a prototype state.
The development of Low-Gain Avalanche Detectors has opened up the possibility of manufacturing silicon detectors with signal larger than that of traditional sensors. In this paper we explore the ...timing performance of Low-Gain Avalanche Detectors, and in particular we demonstrate the possibility of obtaining ultra-fast silicon detector with time resolution of less than 20 picosecond.
A Micromegas (MM) quadruplet prototype with an active area of 0.5 m2 that adopts the general design foreseen for the upgrade of the innermost forward muon tracking systems (Small Wheels) of the ATLAS ...detector in 2018-2019, has been built at CERN and is going to be tested in the ATLAS cavern environment during the LHC RUN-II period 2015-2017. The integration of this prototype detector into the ATLAS data acquisition system using custom ATCA equipment is presented. An ATLAS compatible Read Out Driver (ROD) based on the Scalable Readout System (SRS), the Scalable Readout Unit (SRU), will be used in order to transmit the data after generating valid event fragments to the high-level Read Out System (ROS). The SRU will be synchronized with the LHC bunch crossing clock (40.08 MHz) and will receive the Level-1 trigger signals from the Central Trigger Processor (CTP) through the TTCrx receiver ASIC. The configuration of the system will be driven directly from the ATLAS Run Control System. By using the ATLAS TDAQ Software, a dedicated Micromegas segment has been implemented, in order to include the detector inside the main ATLAS DAQ partition. A full set of tests, on the hardware and software aspects, is presented.
In the upgrade process of the ATLAS detector, the innermost stations of the endcaps (Small Wheels) will be replaced. The New Small Wheel will have two chamber technologies, small-strip Thin Gap ...Chambers and Micromegas, each providing triggering and precision track measurement. Custom front-end Application Specific Integrated Circuits will be used to read and filter information from both types of detectors. In the context of the New Small Wheel data path, the Read Out Controller ASIC is used for handling, preprocessing and formatting the data generated by the VMM upstream chips. The Read Out Controller will concentrate the data streams from 8 VMMs, filter data based on the ATLAS Level-1 trigger which identifies bunch crossings of interest and transmit the data to FELIX via the L1DDC. The Read Out Controller is composed of 8 VMM Capture modules, a cross-bar and 4 sROC modules. The output data is sent via up to 4 serial links with a configurable speed of 80, 160 or 320 Mbps per link.
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