Abstract RDMA communication is an efficient choice for many applications, such as data acquisition systems, data center networking and any other networking application, where high bandwidth and low ...latency are necessary. RDMA can be implemented using a large array of options, which need to be tailored to the needed use case, in order to get optimal results. Aspects such as the effects of using multiple simultaneous connections, using various transport functions such as RDMA Write and RDMA Send and communication models such as sending individual bursts or continuous streams of data will be investigated for implementing RDMA on FPGA devices.
The development of Low-Gain Avalanche Detectors has opened up the possibility of manufacturing silicon detectors with signal larger than that of traditional sensors. In this paper we explore the ...timing performance of Low-Gain Avalanche Detectors, and in particular we demonstrate the possibility of obtaining ultra-fast silicon detector with time resolution of less than 20 picosecond.
The ART Data Driver Card (ADDC) will be used in the ATLAS muon upgrade to process and transmit the Address in Real Time (ART) signals, which are generated by the front end chip (VMM) to indicate the ...location of the first above-threshold event. This ART signal is encoded to represent the address of the first threshold-crossing strip for trigger processing and the magnitude information is not included. The ADDC will be installed on the detector with high radiation and magnetic field thus a custom ASIC (ART ASIC) will be used to receive the ART signals from VMM and do the hit-selection processing. Processed data from ART ASIC will be transmitted out of the detector to the trigger processor through fiber connection. To evaluate the performance of the ADDC before the ART ASIC is produced, an FPGA based prototype was built. This prototype includes most of the major components of the ADDC, while a Xilinx Artix-7 FPGA is used to emulate the ART ASIC. The bench test and integration test results of this prototype will also be described.
The New Small Wheel electronics Iakovidis, G.; Levinson, L.; Afik, Y. ...
Journal of instrumentation,
05/2023, Letnik:
18, Številka:
5
Journal Article
Recenzirano
Odprti dostop
Abstract
The increase in luminosity, and consequent higher
backgrounds, of the LHC upgrades require improved rejection of fake
tracks in the forward region of the ATLAS Muon Spectrometer. The
New ...Small Wheel upgrade of the Muon Spectrometer aims to reduce the
large background of fake triggers from track segments that don't
originate from the interaction point. The New Small Wheel employs
two detector technologies, the resistive strip Micromegas detectors
and the “small” Thin Gap Chambers, with a total of 2.45 million
electrodes to be sensed. The two technologies require the design of
a complex electronics system given that it consists of two different
detector technologies and is required to provide both precision
readout and a fast trigger. It will operate in a high background
radiation region up to about 20 kHz/cm
2
at the expected HL-LHC
luminosity of
ℒ = 7.5 × 10
34
cm
-2
s
-1
. The
architecture of the system is strongly defined by the GBTx data
aggregation ASIC, the newly-introduced FELIX data router and the
software based data handler of the ATLAS detector. The electronics
complex of this new detector was designed and developed in the last
ten years and consists of multiple radiation tolerant Application
Specific Integrated Circuits, multiple front-end boards, dense
boards with FPGA's and purpose-built Trigger Processor boards within
the ATCA standard. The New Small Wheel has been installed in 2021
and is undergoing integration within ATLAS for LHC Run 3. It should
operate through the end of Run 4 (December 2032). In this
manuscript, the overall design of the New Small Wheel electronics is
presented.
The Gigatracker is a hybrid silicon pixel detector developed to track the highly intense NA62 hadron beam with a time resolution of 150
ps (rms). The beam spectrometer of the experiment is composed ...of three Gigatracker stations installed in vacuum in order to precisely measure momentum, time and direction of every traversing particle. Precise tracking demands a very low mass of the detector assembly (
<
0.5
%
X
0 per station) in order to limit multiple scattering and beam hadronic interactions. The high rate and especially the high timing precision requirements are very demanding: two R&D options are ongoing and the corresponding prototype read-out chips have been recently designed and produced in
0.13
μ
m
CMOS technology. One solution makes use of a constant fraction discriminator and on-pixel analogue-based time-to-digital-converter (TDC); the other comprises a delay-locked loop based TDC placed at the end of each pixel column and a time-over-threshold discriminator with time-walk correction technique. The current status of the R&D program is overviewed and results from the prototype read-out chips test are presented.
The NA62 Gigatracker: Detector properties and pixel read-out architectures Fiorini, M.; Carassiti, V.; Ceccucci, A. ...
Nuclear instruments & methods in physics research. Section A, Accelerators, spectrometers, detectors and associated equipment,
12/2010, Letnik:
624, Številka:
2
Journal Article
Recenzirano
The beam spectrometer of the NA62 experiment, named Gigatracker, has to perform single track reconstruction with unprecedented time resolution (150
ps rms) in a harsh radiation environment. To meet ...these requirements, and in order to reduce material budget to a minimum, three hybrid silicon pixel detector stations will be installed in vacuum. An adequate strategy to compensate for the discriminator time-walk must be implemented and R&D investigating two different options is ongoing. Two read-out chip prototypes have been designed in order to compare their performance: one approach is based on the use of a constant-fraction discriminator followed by an on-pixel TDC, while the other one is based on the use of a time-over-threshold circuit followed by a TDC shared by a group of pixels. This paper describes the Gigatracker system, presents the global architectures of both read-out ASICs and reviews the current status of the R&D project.
The increase in luminosity, and consequent higher backgrounds, of the LHC upgrades require improved rejection of fake tracks in the forward region of the ATLAS Muon Spectrometer. The New Small Wheel ...upgrade of the Muon Spectrometer aims to reduce the large background of fake triggers from track segments that are not originated from the interaction point. The New Small Wheel employs two detector technologies, the resistive strip Micromegas detectors and the "small" Thin Gap Chambers, with a total of 2.45 Million electrodes to be sensed. The two technologies require the design of a complex electronics system given that it consists of two different detector technologies and is required to provide both precision readout and a fast trigger. It will operate in a high background radiation region up to about 20 kHz/cm\(^{2}\) at the expected HL-LHC luminosity of \(\mathcal{L}\)=7.5\(\times10^{34}\)cm\(^{-2}\)s\(^{-1}\). The architecture of the system is strongly defined by the GBTx data aggregation ASIC, the newly-introduced FELIX data router and the software based data handler of the ATLAS detector. The electronics complex of this new detector was designed and developed in the last ten years and consists of multiple radiation tolerant Application Specific Integrated Circuits, multiple front-end boards, dense boards with FPGA's and purpose-built Trigger Processor boards within the ATCA standard. The New Small Wheel has been installed in 2021 and is undergoing integration within ATLAS for LHC Run 3. It should operate through the end of Run 4 (December 2032). In this manuscript, the overall design of the New Small Wheel electronics is presented.
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