A new Global Trigger subsystem will be installed in the Level-0 Trigger as part of HL-LHC Upgrade of ATLAS during the upcoming Long-Shutdown 3. It will feature new and improved trigger hardware and ...algorithms, and an increased maximum output rate of 1 MHz. The Global Trigger will run offline-like trigger algorithms on full-granularity data, gathered from several sub-detectors and trigger-processing subsystems. A single Global Common Module (GCM) hardware is implemented across the Global Trigger system to be used as Multiplexer Processor, Global Event Processor and CTP Interface (gCTPi). This common hardware platform method will minimize the complexity of the firmware and simplify the system design and long-term maintenance. The GCM prototype is an ATCA front form factor board with two Xilinx Virtex UltraScale+ FPGA VU13P and one ZYNQ UltraScale+ FPGA ZU19EG and seventeen 25.78125 Gb/s FireFly duplex optical modules on it. The total power consumption of this board must be less than 350 W, and the temperature of the optical modules should be less than 70 °C in the worst case. The VU13Ps serve as algorithms processor nodes such as MUX, GEP and gCTPi, and the ZU19EG with Peta Linux OS running on it, is used as Command/Control/Readout Unit to configure and monitor the board and communicate with the ATLAS Detector Control System (DCS). The development of an ATCA blade with three large FPGAs and about 200 optical links running at 25Gb/s is a very challenging task, and the successful test results have demonstrated this GCM prototype as an advancement of state-of-the-art electronics module design in HEP experiments. This paper presents the hardware design considerations, functionalities, and performance test results of this GCM prototype.
As part of the ATLAS experiment's Phase-II Upgrade, improved trigger hardware and algorithms will be implemented onto a single-level architecture. The global trigger (GT) subsystem is a new firmware ...(FW)-focused project designed to meet stringent requirements from the high-luminosity runs of the large hadron collider (LHC). The global multiplexer (MUX) is the input aggregating stage of the GT; it performs three main tasks: 1) aggregating data from several sources, connected with more than 2300 input fibers, under different protocols; 2) time-multiplexing the incoming data, to sort the packets per bunch-crossing (BC) events, by compensating the relative skews across the various serial input channels; and 3) transmitting, in a round-robin fashion, the sorted BC data to the global event processor (GEP) array, which is the following stage of the GT subsystem and is composed of 48 nodes, each one processing a single BC event. Two MUX FW prototypes for the Global Feature EXtractor (gFEX, part of the liquid argon calorimeter trigger) inputs have been designed, implemented, and validated on a gFEX production board, for up to 72 input and output channels. A four-channel version has been completed with I/O interfaces and validated in a full-chain design, accepting 8b/10b encoded inputs at 11.2 Gb/s and transmitting at 25.78125 Gb/s under Xilinx Aurora 64b/66b protocol. The total latency has been benchmarked in all of its contributing subcomponents and proven to meet the requirements from the Technical Design Report for the Phase-II Upgrade of the trigger and data acquisition system.
Abstract
The High-Luminosity Large Hadron Collider is expected to start operations in the middle of 2027, to deliver more than ten times the integrated luminosity of the Large Hadron Collider Runs ...1–3 combined (up to 4000 fb
−1
). Meeting these requirements poses significant challenges to the hardware design of the trigger and data acquisition system. Global trigger is a new subsystem in the ATLAS phase-II upgrade, which will bring event filter-like capability to the level-0 trigger system. A common hardware platform in Advanced Telecommunications Computing Architecture form factor named Global Common Module is proposed to be configured as processor nodes in the global trigger. To mitigate the risk and simplify the Global Common Module hardware design, a Generic Rear Transition Module is being developed. The Generic Rear Transition Module, which has been implemented with a Xilinx Versal Prime Field Programmable Gate Array and sufficient multi-gigabit transceivers, cannot only achieve system control and communication with the Front-End Link eXchange, but also provide additional processing or readout capacity.
Abstract
The Large Hadron Collider (LHC) at CERN will perform a series of upgrades to allow luminosity increases during the next physics runs expected from 2022 on. These will also significantly ...increase the trigger rates of all the detectors. As part of the ATLAS Phase-I upgrade, the current Small Wheel muon detectors will be replaced with state-of-the-art New Small Wheel (NSW) detectors to cope with the increased luminosity of the LHC. The Address in Real Time Data Driver Card (ADDC) is designed to transmit the trigger data from the resistive Micro-Mesh Gaseous Structure (Micromegas) detectors of the NSW. The ART ASIC on the ADDC is a custom-designed chip to receive the Address in Real Time (ART) signals from the VMM front-end ASIC and perform hit-selection processing. The processed trigger data is then sent to the Trigger Processor (TP) through optical links. A total of 512 ADDCs will be installed on the detector close to the front-end boards. Therefore, those cards must be able to work properly in a high radiation and magnetic field environment. After four rounds of prototyping, the ADDC production was launched in January of 2019. 600 ADDC boards have been produced and tested with an automated test stand. This test setup can simulate the front-end signals and provide "Level-1 Data Driver Card" (L1DDC) functions as well as part of the TP functions. Thus, the ADDC functionality and stability can be verified without the remaining NSW electronics. This paper describes the ADDC hardware prototype development, radiation and integration testing, and the ADDC automated production test procedure.
The New Small Wheel electronics Iakovidis, G.; Levinson, L.; Afik, Y. ...
Journal of instrumentation,
05/2023, Letnik:
18, Številka:
5
Journal Article
Recenzirano
Odprti dostop
Abstract
The increase in luminosity, and consequent higher
backgrounds, of the LHC upgrades require improved rejection of fake
tracks in the forward region of the ATLAS Muon Spectrometer. The
New ...Small Wheel upgrade of the Muon Spectrometer aims to reduce the
large background of fake triggers from track segments that don't
originate from the interaction point. The New Small Wheel employs
two detector technologies, the resistive strip Micromegas detectors
and the “small” Thin Gap Chambers, with a total of 2.45 million
electrodes to be sensed. The two technologies require the design of
a complex electronics system given that it consists of two different
detector technologies and is required to provide both precision
readout and a fast trigger. It will operate in a high background
radiation region up to about 20 kHz/cm
2
at the expected HL-LHC
luminosity of
ℒ = 7.5 × 10
34
cm
-2
s
-1
. The
architecture of the system is strongly defined by the GBTx data
aggregation ASIC, the newly-introduced FELIX data router and the
software based data handler of the ATLAS detector. The electronics
complex of this new detector was designed and developed in the last
ten years and consists of multiple radiation tolerant Application
Specific Integrated Circuits, multiple front-end boards, dense
boards with FPGA's and purpose-built Trigger Processor boards within
the ATCA standard. The New Small Wheel has been installed in 2021
and is undergoing integration within ATLAS for LHC Run 3. It should
operate through the end of Run 4 (December 2032). In this
manuscript, the overall design of the New Small Wheel electronics is
presented.
The upgrades of the LHC accelerator will increase the instantaneous and the integrated luminosity during the data taking in 2019/20 and 2023/24, thus causing increased data and trigger rates. In ...order to cope with the increased muon rate while maintaining high muon detection efficiency the current ATLAS small wheel muon detectors will be replaced with a New Small Wheel (NSW) for high luminosity LHC runs. The NSW will feature two new detector technologies: resistive MicroMegas and small strip Thin Gap Chambers with a total of 2.4 million readout channels. The MicroMegas and TGCs will have common readout paths but separate trigger paths. For the MicroMegas detector, the trigger primitive is the Address in Real Time (ART) signal. The ART Data Driver Card (ADDC) is designed for the MicroMegas detector to process and transmit the trigger data from the front end ASICs to the trigger processor. The ADDC will be located on the detector alongside the front-end electronics, while the trigger processor will be placed away from the high radiation and magnetic field environment. Therefore, it is crucial to thoroughly test the ADDC, since access will be difficult and limited once the NSW is installed. In order to perform a realistic test a dedicated firmware has been developed for the VC707 evaluation card, capable of generating ART signals and reading the ADDC card response that is send to the trigger processor. The FPGA can validate the ADDC response in real time and signify any errors found. A software library has also been developed, in order to control and monitor the test setup using a computer. Finally, a user interface will be developed to simplify and automate the test process.
In order to benefit from the expected increase in luminosity of the upgraded LHC accelerator, the innermost station in the forward region of the ATLAS Muon Spectrometer will be replaced by the New ...Small Wheel, (NSW) currently under construction. NSW features two new detector technologies (resistive Micromegas detectors, (MM) and small strip Thin Gap Chambers, (sTGC)) comprising ~ 2.4 × 10 6 readout channels. The large number of readout channels, the high data rates and the harsh conditions, under which the NSW will operate, pose significant challenges to its trigger and data acquisition system. The Level-1 Data Driver Card (L1DDC) boards are part of the on NSW detector electronics and mainly consist of high radiation and magnetic field tolerant custom made ASICs. Three different types of L1DDC boards have been developed; two for the readout chain of the MMs and sTGCs and one for the trigger electronics chain of the sTGCs. Over 97% of the 1184 L1DDC boards (572 for the MM and 612 for the sTGC detector technologies) that have been tested at four testing sites are found to operate according to their specifications.
The increase in luminosity, and consequent higher backgrounds, of the LHC upgrades require improved rejection of fake tracks in the forward region of the ATLAS Muon Spectrometer. The New Small Wheel ...upgrade of the Muon Spectrometer aims to reduce the large background of fake triggers from track segments that are not originated from the interaction point. The New Small Wheel employs two detector technologies, the resistive strip Micromegas detectors and the "small" Thin Gap Chambers, with a total of 2.45 Million electrodes to be sensed. The two technologies require the design of a complex electronics system given that it consists of two different detector technologies and is required to provide both precision readout and a fast trigger. It will operate in a high background radiation region up to about 20 kHz/cm\(^{2}\) at the expected HL-LHC luminosity of \(\mathcal{L}\)=7.5\(\times10^{34}\)cm\(^{-2}\)s\(^{-1}\). The architecture of the system is strongly defined by the GBTx data aggregation ASIC, the newly-introduced FELIX data router and the software based data handler of the ATLAS detector. The electronics complex of this new detector was designed and developed in the last ten years and consists of multiple radiation tolerant Application Specific Integrated Circuits, multiple front-end boards, dense boards with FPGA's and purpose-built Trigger Processor boards within the ATCA standard. The New Small Wheel has been installed in 2021 and is undergoing integration within ATLAS for LHC Run 3. It should operate through the end of Run 4 (December 2032). In this manuscript, the overall design of the New Small Wheel electronics is presented.
