A high-speed, one-dimensional detector array for electrons and UV/X-ray photons has been developed. The detector is capable of handling the high countrates encountered in at third generation ...synchrotron radiation sources and is free from nonlinearity problems present in charge coupled device (CCD) detectors. Electrons are counted by a configuration of microchannel plates, an array of charge collection electrodes, and custom-designed integrated circuits (IC) assembled on a ceramic hybrid. The charges are collected on 768 strips with a 48 /spl mu/m pitch that are wire-bonded to 6 pairs of signal processing ICs. Each front-end IC has 128 channels of amplifiers (peaking time 25 ns) and discriminators. The pulse-pair resolution is 50 ns leading to a maximum linear countrate/channel of 2 MHz. The second, custom-designed IC features 24-b buffered counters and a serial link for the transfer of commands and data. A possible deadtime-less readout of all channels in 150 /spl mu/s opens the door to time resolved experiments. The complete detector system includes the high-voltage power supply, a field programmable gate array (FPGA)-based data acquisition system, and supporting software. Special care has been taken to insure reliable operation in an ultra-high vacuum environment. The detector architecture and design is described and measured performance characteristics such as spatial resolution and count-rate linearity are presented.
We are developing a prototype X-ray detection system that should be ideal for many types of synchrotron science. X-rays are captured directly in thick, high-resistivity, single-crystal, silicon pixel ...sensors. Unlike other X-ray detectors, which have a substantial dead area around their borders, these have "active edges"-edges formed from electrodes in the third dimension, perpendicular to the top and bottom surfaces, with full sensitivity to within a micron of the physical border. Each sensor is 0.96 mm/spl times/0.96 mm, having a 64/spl times/64 two-dimensional array of 150 /spl mu/m pixels. Behind each sensor, a custom CMOS readout chip is bump-bonded to the sensor. It provides high-speed (64/spl mu/s/full-array) readout of each pixel, with a dead time for each row, during pixel reset, of 1 /spl mu/s. On three edges, it lies completely hidden behind the sensor. A 3 mm wide region on the remaining edge of each CMOS chip contains readout circuits and connections. Here it protrudes beyond the sensor edge, but is covered by the active region of a neighboring sensor module in an array similar to that of shingles on a roof. Sensor units can be easily arrayed to cover large areas. The readout chip has 128 ADCs and, for each pixel, a charge amplifier. To save fabrication costs, the prototype readout has just 8/spl times/64 pixels. Using pulse heights, we should be able to combine signals when X-rays share charge between adjacent pixels. We have already made accurate quantum-counts of 0 to 7 X-ray events/pixel during each 64 /spl mu/s readout cycle.
MCC: the Module Controller Chip for the ATLAS Pixel Detector Beccherle, R; Darbo, G; Gagliardi, G ...
Nuclear instruments & methods in physics research. Section A, Accelerators, spectrometers, detectors and associated equipment,
10/2002, Letnik:
492, Številka:
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Journal Article
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In this article we describe the architecture of the Module Controller Chip for the ATLAS Pixel Detector. The project started in 1997 with the definition of the system specifications. A first ...fully-working rad-soft prototype was designed in 1998, while a radiation hard version was submitted in 2000. The 1998 version was used to build pixel detector modules. Results from those modules and from the simulated performance in ATLAS are reported. In the article we also describe the hardware/software tools developed to test the MCC performance at the LHC event rate.
We report on the design and construction of a next-generation, ultrahigh-speed, one-dimensional detector for electron and other spectroscopies, and discuss some first experimental results obtained ...with it. This detector is capable of recording spectra over 768 channels with ∼1.5 channels (∼75
μm) resolution and with good linearity up to countrates of >1
MHz per channel or >1
GHz overall. In first experiments with it, photoelectron spectra spanning several hundred channels of resolution have been obtained in as little as 50
ms; with future system improvements, this time should be reduced to 150
μs. The data obtained include rapid X-ray photoelectron diffraction scans and time-resolved core-level observations of a surface reaction process. This detector should open up several types of new experiment, including more rapid real-time observations of surface reaction kinetics by means of inner-shell spectroscopies.
We present the architecture, critical design issues, and performance measurements of PETRIC, a 64-channel mixed signal front-end integrated circuit for reading out a photodiode array coupled with ...Lu/sub 2/SiO/sub 5/Ce scintillator crystals for a medical imaging application: positron emission topography. Each channel consists of a low-noise charge-sensitive preamplifier, an RC-CR pulse shaper and a winner-take-all multiplexer that selects the channel with the largest input signal. Triggered by an external timing signal, a switch opens and a capacitor stores the peak voltage of the winner channel. The shaper peaking time is adjustable by means of external current inputs over a continuous range of 0.7 /spl mu/s to 9 /spl mu/s. Power consumption is 5.4 mW per channel, measured equivalent noise charge at 1-/spl mu/s peaking time, zero leakage current is 33 rms electrons plus 7.3 rms electrons per pF of input capacitance. Design is fabricated in 0.5-/spl mu/m 3.3-V complementary metal-oxide semiconductor technology.
A fast low noise, limited power, radiation-hard front-end chip was developed for reading out the Atlas Pixel Silicon Detector. As in the past prototypes, every chip is used to digitize and read out ...charge and time information from hits on each one of its 2880 inputs. The basic column readout architecture idea was adopted and modified to allow a safe transition to quarter micron technology. Each pixel cell, organized in a 16018 matrix, can be independently enabled and configured in order to optimize the analog signal response and to prevent defective pixels from saturating the readout. The digital readout organizes hit data coming from each column, with respect to time, and output them on a low-level serial interface. A considerable effort was made to design state machines free of undefined states, where single-point defects and charge deposited by heavy ions in the silicon could have led to unpredicted forbidden states.
A new analog pixel front-end cell has been developed for the ATLAS detector at the future Large Hadron Collider (LHC) at the European Laboratory for Particle Physics (CERN). This analog cell has been ...submitted in two commercial 0.25 mu m CMOS processes (in an analog test chip format), using special layout techniques for radiation hardness purposes. It is composed of two cascaded amplifiers followed by a fast discriminator featuring a detection threshold within the range of 1000 to 10000 electrons. The first preamplifier has the principal role of providing a large bandwidth, low input impedance, and fast rise time in order to enhance the time-walk and crosstalk performance, whereas the second fully differential amplifier is aimed at delivering a sufficiently high-voltage gain for optimum comparison. A new do feedback concept renders the cell tolerant of sensor leakage current up to 300 nA and provides monitoring of this current. Two 5-bit digital-to-analog converters tolerant to single-event upset have been implemented for threshold and recovery-time pixel-to-pixel matching purposes. Special attention has been paid to the power-supply rejection ratio to minimize sensitivity to pickup. The complete cell dissipates 30 mu W, occupies an area of 5090 mu m super(2) and is operated with a single 1.6-V power supply. Measurements of two test chips are presented.
The ABCD design is a single chip implementation of the binary readout architecture for silicon strip detectors in the ATLAS semiconductor tracker. The prototype chip has been manufactured ...successfully in the DMILL process. In the paper we present the design of the chip and the measurement results. The basic analogue performance of the ABCD design has been evaluated using a prototype SCT module equipped with the ABCD chips. The digital performance has been evaluated using a general purpose IC tester. The measurements confirmed that all blocks of the ABCD design are fully functional and the chips meet all basic requirements of the SCT. Wafer screening has been performed using a customised wafer tester.
We present a compact, configurable scintillation camera employing a maximum of 16 individual 64-pixel imaging modules resulting in a 1024-pixel camera covering an area of 9.6 cm/spl times/9.6 cm. The ...64-pixel imaging module consists of optically isolated 3 mm/spl times/3 mm/spl times/5 mm CsI(Tl) crystals coupled to a custom array of Si p-i-n photodiodes read out by a custom integrated circuit (IC). Each imaging module plugs into a readout motherboard that controls the modules and interfaces with a data acquisition card inside a computer. For a given event, the motherboard employs a custom winner-take-all IC to identify the module with the largest analog output and to enable the output address bits of the corresponding module's readout IC. These address bits identify the "winner" pixel within the "winner" module. The peak of the largest analog signal is found and held using a peak detect circuit, after which it is acquired by an analog-to-digital converter on the data acquisition card. The camera is currently operated with four imaging modules in order to characterize its performance. At room temperature, the camera demonstrates an average energy resolution of 13.4% full-width at half-maximum (FWHM) for the 140-keV emissions of /sup 99m/Tc. The system spatial resolution is measured using a capillary tube with an inner diameter of 0.7 mm and located 10 cm from the face of the collimator. Images of the line source in air exhibit average system spatial resolutions of 8.7- and 11.2-mm FWHM when using an all-purpose and high-sensitivity parallel hexagonal holes collimator, respectively. These values do not change significantly when an acrylic scattering block is placed between the line source and the camera.
We characterize the performance of a complete 64-pixel compact gamma camera imaging module consisting of optically isolated 3 /spl times/ 3 /spl times/ 5 mm/sup 3/ CsI(Tl) crystals coupled to a ...custom array of low-noise Si PIN photodiodes read out by a custom IC. At 50-V bias, the custom 64-pixel photodiode arrays demonstrate an average leakage current of 28 pA per 3 /spl times/ 3 mm/sup 3/ pixel, a 98.5% yield of pixels with <100 pA leakage, and a quantum efficiency of about 80% for 540-nm CsI(Tl) scintillation photons. The custom 64-channel readout IC uses low-noise preamplifiers, shaper amplifiers, and a winner-take-all (WTA) multiplexer. The IC demonstrates maximum gain of 120 mV/1000 e/sup -/, the ability to select the largest input signal in less than 150 ns, and low electronic noise at 8-/spl mu/s peaking time ranging from 25 e/sup -/ rms (unloaded) to an estimated 180 e/sup -/ rms (photodiode load of 3 pF, 50 pA). At room temperature, a complete 64-pixel detector module employing a custom photodiode array and readout IC demonstrates an average energy resolution of 23.4% FWHM and an intrinsic spatial resolution of 3.3-mm FWHM for the 140-keV emissions of /sup 99m/Tc. The construction of an array of such imaging modules is straightforward; hence this technology shows strong potential for numerous compact gamma camera applications, including scintimammography.
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