Hold timing closure and scan power are major concerns for any design. Hold closure for scan shift operation generally causes addition of buffers in the data path between flip-flops. This results in ...increased gate count that will toggle during the functional mode of operation thereby resulting in an increase in functional power. Scan operation also causes higher switching activity due to high toggling in a given test cycle. There are two components of power i.e. peak power and average power. Peak power increases IR-drop in the design, thereby reducing the voltage across the transistor and can lead to failure. In this paper we will present a modified flip-flop architecture that will serve two purposes i.e. enabling hold timing closure across process, voltage, temperature and reducing peak power during scan shift operation with minimal impact to functional timing and area. The modified flip-flop will introduce a half cycle delay in the data path invariant of process, voltage, temperature thereby easing hold closure. Test time and coverage are not impacted by the same. Existing ATPG tool generated pattern can be applied with this scheme. This approach reduces peak power close to 50% and reduces hold buffer area close to 40% in a given design.
It is well-known that complex SOCs with RF and embedded power management (PM) modules require significant post manufacturing calibration to ensure that the device meets the design specifications. ...These calibrations are carried out by setting the register bits (which in turn help to finely adjust the parameters of the components inside the module containing these registers), a process commonly termed as trim. Not only must these calibrations precede any other manufacturing test operation, but they also require analog measurements and consume significant ATE resources and hence test time. As a result, it is commonly understood and observed that the calibration trim for such SOCs with embedded RF and PM is often comparable to the SOC test time itself. This paper presents some crucial investigations into one such 45 nm multi-core RF SOC designed at Texas Instruments. Its main contributions are: (i) The various trim operations are analyzed for the incurred test times and incurred ATE resources. (ii) Corresponding to each such operation, trim test time minimization techniques are proposed and experimental data on the accrued benefits is presented. (iii) A comprehensive hardware trim BIST controller is described, which enables trim automation and further optimization in complex SOCs. Together, these investigations provide a recipe for efficiently performing trims in complex mixed-signal SOCs with reduced test times and higher ATE enabled multi-site.
Towards Single Pin Scan for Extremely Low Pin Count Test Kawoosa, Mudasir S.; Mittal, Rajesh K.; Jalasuthram, Maheedhar ...
2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID),
2018-Jan.
Conference Proceeding
Design-for-Testability (DFT) techniques for test cost reduction of digital circuits rely on efficient deployment of scan test through smart DUT (device under test) partitions, matching of scan test ...I/O needs to the DUT needs for increased scan data throughput, and optimal test pattern generation methods. The test cost is further reduced by testing multiple devices in parallel using the same set of ATE resources. As a result, the number of scan pins available in a DUT for test application is reduced. The need for managing different DUT partitions and ensuring that the scan I/O interface matches with the DUT requirements further aggravates the need for scan test pins. In this paper, a generic methodology for reduced pin count scan test is presented. Specific solutions are described for internal generation of all scan mode control signals, e.g. scan enable, clock control, X-mask control, switching between slow speed shift clock and high speed capture clock, etc., across one or more DUT partitions. It is shown how this method can ultimately lead to a single pin scan test solution. These methods have been implemented in cost sensitive SOC designs and, as a result, the scan test time has been reduced by 2x - 3x over what has been achieved using other aggressive test cost reduction methods for scan compression. These methods are also independent of the specific scan compression solution used.
Tutorial T10: Post - Silicon Validation, Debug and Diagnosis Mishra, Prabhat; Fujita, Masahiro; Singh, Virendra ...
2013 26th International Conference on VLSI Design and 2013 12th International Conference on Embedded Systems,
2013-Jan., 20130101
Conference Proceeding, Journal Article
Summary form only given, as follows. The complete presentation was not made available for publication as part of the conference proceedings. Drastic increase in design complexity along with the ...emergence of new failure mechanisms in the nanometer regime has led to significant increase in the complexity of verification, validation, and debug of integrated circuits. In spite of extensive efforts, it is not always possible to detect all the functional errors and electrical faults during pre-silicon validation. Post-silicon validation is used to detect design flaws including the escaped functional errors as well as electrical faults. In this tutorial, we will provide a comprehensive coverage of both fundamental concepts and recent advances in post-silicon validation, debug and diagnosis. The tutorial presenters (3 industry experts and 3 faculty members) will provide unique perspectives on both academic research and industrial practices. First, we will discuss various challenges associated with post-silicon validation and debug. Next, we will describe various techniques for automated generation of directed tests to activate both functional errors and electrical faults. We will cover recent advances in observability enhancement through signal selection and low-overhead trace hardware design. We will also describe various state-of-the-art post-silicon debug approaches for modern microprocessors and SoC designs. Next, we will present examples of real-life design failures, and successful debug scenarios in industrial settings. Finally, we will conclude the tutorial with discussion on emerging issues and future directions for successful postsilicon validation and debug.
Objective: To describe a case involving the cryopreservation of testis tissue retrieved from a 15-year-old male teenager with Klinefelter’s syndrome.
Design: Case report.
Setting: An academic medical ...center.
Patient(s): A 15-year-old boy with Klinefelter’s syndrome.
Intervention(s): Microsurgical testis sperm extraction with cryopreservation of harvested tissue.
Main Outcome Measure(s): Spermatozoa within testis tissue.
Result(s): Successful extraction and cryopreservation of three vials of sperm-containing testis tissue. No effect on subsequent testosterone levels.
Conclusion(s): Testis tissue extraction in the adequately virilized but azoospermic young male with 47, XXY Klinefelter’s syndrome may be a strategy to preserve future biological paternity.
Wireless connectivity SOCs integrate multi-band radios on a single chip. Examples include WLAN 802.11 ("A" band or "BG" band), Bluetooth, Global Positioning System (GPS) and FM (Frequency Modulation) ...transmitters and receivers. It has been observed the cost of testing these RF components constitutes about 40% of the total cost of testing such an SOC. Reduction of this test cost is, therefore, important. The usage of multiple radios on a single chip provides the option of testing all of them concurrently. The unique functionality and different frequency bands of these radio modules however, prevent blind (unconstrained) parallelism, something which is ubiquitously possible for digital logic and memory modules. Additionally, the ability to test multiple dies in parallel (multi-site testing) and the ability to adopt low-cost tester platforms must also be considered. In this presentation, a case study of a complex SOC with four such radio modules is presented. It is shown how their concurrent test can be planned, together with high levels of multi-site with a low-cost tester platform. Various considerations and tradeoffs in the adoption of this solution are discussed, keeping in mind co-existence and coupling issues when these radios operate in parallel. The software BIST solution (where firmware is executed on a host processor inside the RF module) used to enable such concurrency is also explained, together with the design support required.
This dissertation examines the philosophy of history espoused by Virgil in the Aeneid. On the one hand this involves locating the philosophical inspiration behind Virgil's diverse references to ...temporality. On the other hand, it involves considering how Virgil interpreted the momentous historical events that had occurred in his own lifetime. With regard to this second point, I have taken the constructive approach of isolating aspects of the Aeneid that interpret contemporary history, and comparing them to several of Augustus' public displays from the period following Actium that respond to the same historical stimuli. This approach allows us to see the tremendous rapport that existed between the way these two conceived of history and historical agency, and indicates that Virgil was much more supportive of Augustus than some have supposed. The two most important philosophical influences on Virgil's conception of history are Stoicism and Pythagoreanism. With its doctrine of ekpyrosis, the former offered Virgil a model of history that identified destruction with creation, and thus complemented his interpretation of time as a basically sacrificial process. This latter feature is one of the most important aspects of the poem, and I devote significant attention to its presence and function in the Aeneid. This sacrificial conception of history produces a tension that underlies many of the poem's pivotal moments; Virgil establishes this tension in such a way that it can only be resolved by a permanent escape from temporality. Such an escape was offered by the form of Pythagoreanism that he would have known, and for this reason it is the primary influence behind Virgil's conception of the afterlife. Virgil's reliance on these two traditions has led to the existence of two 'arcs' in the narrative, and I argue that each of these culminates in a 'Golden Age.' Part of his reason for doing this was to accommodate the genuine progress that he had witnessed in his lifetime, largely in the political sphere through Octavian/Augustus. But even the latter, as I argue, was intent upon maintaining the distinction between the temporal and eternal worlds.
Towards adaptive test of multi-core RF SoCs Mittal, Rajesh; Balasubramanian, Lakshmanan; Kumar Y.B., Chethan ...
2013 Design, Automation & Test in Europe Conference & Exhibition (DATE),
2013-March
Conference Proceeding
This paper discusses how adaptive test techniques can be applied to multi-core RF SoCs, together with design implementation and test challenges. Various techniques specific to RF circuits covering ...calibration trims, power management modules, co-existence issues, concurrent testing, and test measurements are explained. Results on different designs are presented. Together, they highlight the need and scope of adaptive test for RF circuits, and share a new dimension in the test of multi-core circuits, under different constraints of design, test and test equipment.
Mixed signal SOCs with integrated RF and power management modules have some distinct requirements associated with them. They are often used in portable and battery operated consumer applications, ...which are extremely cost and power sensitive. This translates into a few unique design and test constraints on the amount of DFT logic integrated, the permissible test time, and power-up of individual modules in the SOC. In this paper, we propose some novel DFT and test techniques which have been devised keeping in mind these constraints, and illustrate how test cost has been significantly reduced in such cost and power constrained mixed signal SOCs. The paper discusses three significant components of the test time and techniques for their reduction through smarter DFT and BIST: (i) RF tests in multiple radio modules, (ii) test and calibration of complex power management logic and voltage regulators, and (iii) improved scan ATPG for all the digital logic. These techniques are being integrated into Texas Instruments' embedded SOCs designed for such portable application, resulting in an overall test cost reduction by half over the previous generation of such SOCs.
It has been proposed that in hydrogen bonded systems, such as ice, charge transport occurs through a process involving two types of defects (the so-called orientational and ionic defects) in the ...proton sublattice. We have constructed simple models which allow us to investigate the formation and motion of both ionic and orientational defects (separately) in a one dimensional chain of hydrogen bonded sites. The models incorporate a classical lattice Hamiltonian and a modified tight binding electronic Hamiltonian in which site energies are dependent on lattice displacements. The model has been used to study the origin of the proton double well potential reflecting two degenerate ground-state phases of such a chain. Numerical simulations of the dynamics have been carried out on finite chains in both the absence and presence of an electric field. More insight is gained into the ionic defect studies by incorporating both a stationary and a mobile oxygen sublattice. Thermal effects have also been considered. The latter calculations have been performed using the Nose-Hoover thermostat, in which an additional degree of freedom has been introduced to connect the physical system to a heat bath. We find that inclusion of a mobile oxygen sublattice along with thermal effects allows us to reproduce recent experimentally observed mobilities.
