The electroencephalogram (EEG) is a non-invasive and affordable technique to study the brain activity during wakefulness and especially during sleep. The current trend on sleep analysis focuses on ...its dynamic organization described in the cyclic alternating pattern (CAP) paradigm. This paradigm looks to the EEG microstructure, gives attention to the short duration EEG phenomena instead of the traditional global view of fixed epochs of 20 or 30 seconds, heralded by the Rechtschaffen and Kales (R&K) classification. The CAP paradigm not only cares about the short duration events but also models its periodic activity, providing thus, important information on EEG synchrony modulation in the sleep process. These periodic activities are characterized by repeated spontaneous and or evoked EEG activations or transient responses (A phases), at intervals up to one minute emerged from the background activity (B phases). In a previous work we proposed an automatic detector and classifier of A phases in sleep EEG, where wavelet transforms is used to analyze the sleep EEG signal in the time-frequency domain, in order to separate the signal power in different and physiologically relevant frequency bands. The CAP A phases characteristics described in the classification Atlas is used in the design of the structure and the starting set of parameters of the detector and classifier. The objective of this work is to use genetic algorithm to tune the parameters of the detector and classifier. Excerpts of all night sleep recordings of a group of volunteers are used in the tuning and testing. Results are compared with visual and other automatic classification.
Hardware voters are bit voters computing a majority of n input bits. An m-out-of-n hardware bit voter is a circuit with n bit inputs, and 1 bit output y, such that y=1 if at least m-out-of-n inputs ...bits have the value 1. A hardware voter can be constructed as two level AND-OR (equivalently OR-AND and other structures) using CMOS VLSI technology. The goal of the paper is to present reliability estimations, failure modes and effects and criticality analysis (FMECA) of voting networks at the transistor level, in CMOS VLSl implementation. FMECA is performed using the functional tree of the system, representing the data flow from the lowest level functional block up to the higher level functional blocks. The main idea of this research is to identify the best designs of voting circuits in terms of reliability parameters and to identify their critical failures and effects.
