VMM1-An ASIC for Micropattern Detectors De Geronimo, G.; Fried, J.; Shaorui Li ...
IEEE transactions on nuclear science,
06/2013, Letnik:
60, Številka:
3
Journal Article
Recenzirano
Odprti dostop
We present VMM1, the first prototype of a family of front-end ASICs designed for the ATLAS muon upgrade. The ASIC will operate with MICROMEGAS and TGC detectors, providing charge and timing ...measurements along with other features including sub-hysteresis discrimination, address of the first event in real time, and digital output per channel for Time-over-Threshold measurements. The shaper, designed via the concept of Delayed Dissipative Feedback (DDF), supports analog dynamic ranges in excess of 10 \thinspace000. With a capacitance of 200 pF and a nominal peaking time of 25 ns, the ASIC offers resolution of charge and timing better than 1 fC and 1 ns, respectively, for input charges up to 2 pC. Designed in a commercial 130 nm technology it dissipates about 4.5 mW per channel.
Front-End ASIC for a Liquid Argon TPC De Geronimo, G; D'Andragora, A; Shaorui Li ...
IEEE transactions on nuclear science,
06/2011, Letnik:
58, Številka:
3
Journal Article
Recenzirano
We present a front-end application-specific integrated circuit (ASIC) for a wire based time-projection-chamber (TPC) operating in liquid Argon (LAr). The LAr TPC will be used for long baseline ...neutrino oscillation experiments. The ASIC must provide a low-noise readout of the signals induced on the TPC wires, digitization of those signals at 2 MSamples/s, compression, buffering and multiplexing. A resolution of better than 1000 rms electrons at 200 pF input capacitance for an input range of 300 fC is required, along with low power and operation in LAr (at 87 K). We include the characterization of a commercial technology for operation in the cryogenic environment and the first experimental results on the analog front end. The results demonstrate that complementary metal-oxide semiconductor transistors have lower noise and much improved dc characteristics at LAr temperature. Finally, we introduce the concept of "1/f equivalent" to model the low-frequency component of the noise spectral density, for use in the input metal-oxide semiconductor field-effect transistor optimization.
An instrumentation channel is designed, implemented, and tested in a 0.5-μm SiGe BiCMOS process. The circuit features a reconfigurable Wheatstone bridge network that interfaces an assortment of ...external sensors to signal processing circuits. Also, analog sampling is implemented in the channel using a flying capacitor configuration. The analog samples are digitized by a low-power multichannel A/D converter. Measurement results show that the instrumentation channel supports input signals up to 200 Hz and operates across a wide temperature range of -180°C to 125°C. This work demonstrates the use of a commercially available first generation SiGe BiCMOS process in designing circuits suitable for extreme environment applications.
The choice between cold and warm electronics (inside or outside the cryostat) in very large LAr TPCs (>5-10 ktons) is not an electronics issue, but it is rather a major cryostat design issue. This is ...because the location of the signal processing electronics has a direct and far reaching effect on the cryostat design, an indirect effect on the TPC electrode design (sense wire spacing, wire length and drift distance), and a significant effect on the TPC performance. All these factors weigh so overwhelmingly in favor of the cold electronics that it remains an optimal solution for very large TPCs. In this paper signal and noise considerations are summarized, the concept of the readout chain is described, and the guidelines for design of CMOS circuits for operation in liquid argon (at ∼89 K) are discussed.
Measurements of the first prototype VMM1 ASIC designed at Brookhaven National Laboratory in 130nm CMOS and fabricated in spring 2012 are presented. The 64-channel ASIC features a novel design for use ...with several types of micropattern gas detectors. The data driven system measures peak amplitude and timing information in tracking mode including sub-threshold neighbors and first channel hit address in trigger mode. Several programmable gain and integration times allows the flexibility to work with Micromegas, Thin Gap Chambers (TGCs), and Gas Electron Multiplier (GEM) detectors. The IC design and features are presented along with measurements characterizing the performance of the VMM1 such as noise, linearity of the response, time walk, and calibration range.
VMM1 - An ASIC for micropattern detectors De Geronimo, Gianluigi; Fried, Jack; Shaorui Li ...
2012 IEEE Nuclear Science Symposium and Medical Imaging Conference Record (NSS/MIC),
2012-Oct.
Conference Proceeding
Odprti dostop
We present VMM1, the first prototype of a family of front-end ASICs designed for the ATLAS muon upgrade. The ASIC will operate with MICRO MEG AS and TGC detectors providing charge and timing ...measurements along with a number of features including sub-hysteresis discrimination, address of the first event in real time, and digital output per channel for Time-over-Threshold measurements. The shaper, designed using the concept of Delayed Dissipative Feedback (DDF), allows analog dynamic ranges in excess of 10,000. With a capacitance of 200 pF and a nominal peaking time of 25 ns it can provide charge and timing resolution below 1 fC and Ins respectively, for input charges up to 2 pc. Designed in a commercial 130 nm technology it dissipates about 4.5 mW per channel.
A novel current-mode multi-channel integrating ADC Nambiar, Neena; Blalock, Benjamin J.; Nance Ericson, M.
Analog integrated circuits and signal processing,
05/2010, Letnik:
63, Številka:
2
Journal Article
Recenzirano
A novel current-mode multi-channel ADC has been designed, fabricated, and characterized in a 0.5-μm bulk CMOS process. The ADC utilizes a Wilkinson architecture with current-mode comparators and is ...capable of supporting multiple channels with an input current range of 10–150 μA. The main blocks in the ADC include a current ramp generator with active current mirrors, multiple current comparators, and a 12-bit Gray code counter. A novel architecture Gray code counter supports high frequency counting. For sampling rates up to 10 kHz, measurement results are presented including integral nonlinearity and differential nonlinearity. A per-channel power consumption of less than 2 mW using a Wilkinson architecture with 4 channels was observed. This work represents the first published current-mode, multi-channel Wilkinson ADC.
The LBNE Project is developing a design for multiple 20 kiloton liquid argon (LAr) time projection chambers to be used as the far detector for the Long Baseline Neutrino Experiment. An essential ...component of this design is a complete electronic readout system designed to operate in LAr (at 90K). This system is being implemented as a CMOS ASIC, in 180nm commercial technology, that will provide low-noise readout of the signals induced on the TPC wires, digitization of those signals at 2 MS/s, zero-suppression, buffering and output multiplexing to a small number of cryostat feed-throughs. A resolution better than 1000 rms electrons at 200 pF input capacitance for an input range of 300 fC is required, along with low power (<15mW/channel) and operation in LAr with a lifetime greater than 15 years. An analog-only frontend has been successfully completed and fully evaluated, and will be used in the MicroBooNE LAr TPC. A prototype of the digital section has been fabricated and is being evaluated. The results demonstrate that CMOS transistors have lower noise and much improved dc characteristics at LAr temperature. We will describe the progress to date and plans for the remaining development.
Front-end ASIC for a liquid argon TPC De Geronimo, G.; D'Andragora, A.; Shaorui Li ...
IEEE Nuclear Science Symposuim & Medical Imaging Conference,
2010-Oct.
Conference Proceeding
We introduce a front-end application specific integrated circuit (ASIC) for a wire based Time-Projection-Chamber (TPC) operating in liquid Argon (LAr). The LAr TPC will be used for long baseline ...neutrino oscillation experiments. The ASIC must provide low-noise readout of the signals induced on the TPC wires, digitization of those signals at 2 MS/s, compression, buffering and multiplexing. A resolution better than 1000 rms electrons at 200 pF input capacitance for an input range of 300 fC is required, along with low power and operation in LAr (at 87 K). We present the characterization of a commercial technology for operation in cryogenic environment and the first experimental results on the analog front-end. The results demonstrate that CMOS transistors have lower noise and much improved dc characteristics at LAr temperature. Finally, we introduce the concept of "1/f equivalent" to model the low-frequency component of the noise spectral density, for use in the input MOSFET optimization.
Thesis (M.S.)--University of Tennessee, Knoxville, 2004.
Title from title page screen (viewed Jan. 13, 2005). Thesis advisor: Daniel B Koch. Document formatted into pages (x, 88 p. : ill. (some ...col.)). Vita. Includes bibliographical references (p. 60-63).
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