In this paper, the non-ideal factors, which include spatial noise and temporal noise, are analyzed and suppressed in the high-speed spike-based image sensor, which combines the high-speed scanning ...sequential format with the method that uses the interspike time interval to indicate the scene information. In this imager, spatial noise contains device mismatch, which results in photo response non-uniformity (PRNU) and the non-uniformity of dark current. By multiplying the measured coefficient matrix the photo response non-uniformity is suppressed, and the non-uniformity of dark current is suppressed by correcting the interspike time interval based on the time interval of dark current. The temporal noise is composed of the shot noise and thermal noise. This kind of noise can be eliminated when using the spike frequency to restore the image. The experimental results show that, based on the spike frequency method, the standard deviation of the image decreases from 18.4792 to 0.5683 in the uniform bright light by using the calibration algorithm. While in the relatively uniform dark condition, the standard deviation decreases from 1.5812 to 0.4516. Based on interspike time interval method, because of time mismatch and temporal noise, the standard deviation of the image changes from 27.4252 to 27.4977 in the uniform bright light by using the calibration algorithm. While in the uniform dark condition, the standard deviation decreases from 2.361 to 0.3678.
In this paper, a 120 × 45 global shutter high speed time delay integration (TDI) CMOS image sensor with pipelined charge transfer pixel (PCT-pixel) is presented. Offset free and low noise pipelined ...signal accumulation are achieved by the PCT-pixel, and a novel layout is also proposed to increase the equivalent photosensitive area's fill factor of the proposed pixel. Due to the parallelism of the proposed PCT-pixel, global shutter exposure method is applied in this sensor, which can eliminate nonsynchronous signal capturing problem. The proposed TDI sensor is implemented in a 0.11-μm one-poly three-metal CMOS image sensor technology with a line rate of 100 KHz, a PCT-pixel size of 30 × 15 μm 2 , and a fill factor of 43.5%. Measurement results show that the sensor can achieve a maximum sensitivity of 95 V/lux × sec and an energy consumption of 0.12 nJ/pixel. Measured signal-to-noise ratio boost value follows theoretical value well. The proposed sensor has the potential to achieve high scanning speed and high TDI stage while costing less power and silicon area.
This letter proposes a novel high dynamic range (
HDR
) pixel using lateral overflow integration capacitor (LOFIC) and adaptive feedback structure. Through detailed analysis of the voltage feedback ...mechanism, the conversion gain (
CG
), full well capacity (
FWC
) and dynamic range (
DR
) performances of the feedback LOFIC pixel are analytically expressed. The verification results reveal that the equivalent
FWC
of the feedback LOFIC pixel is 1.89 times of conventional LOFIC pixel, and the
DR
extension is 5.5 dB. Based on 110 nm CMOS process, a 5.0 µm pixel layout is presented, using 13.3 fF capacitance to achieve 83 ke-
FWC
and 102.8 dB
DR
, which are 44 ke- and 97.3 dB of conventional LOFIC pixel under the same design conditions. This also demonstrates that the feedback LOFIC pixel can reduce the dependence of extended
DR
on capacitor area, and can be used as a reference for
HDR
pixels design.
This paper proposed a high‐speed target tracking algorithm based on the pulse‐sequence‐based image sensor. The algorithm separates the target from the background through the statistical distribution ...of the pulses in a single frame of data. In order to achieve more accurate target tracking, the phenomenon of image lag in the process of capturing the high‐speed moving target is studied. The positioning deviation is compensated by estimating the image lag length of the moving target. The algorithm is implemented with pipeline processing on field‐programmable gate array (FPGA). The positioning accuracy of the algorithm is verified with input data from a pulse‐sequence image sensor model. The verification results show that the maximum position deviation of the target at different speeds is 0.94 pixels. In the experiment of tracking a 40 m/s moving ball, this algorithm can provide real‐time position information within 44 ns.
An adaptive thresholds algorithm is proposed in this letter, which is used to determine the global optimal thresholds for multi-bit quanta image sensor (MB-QIS). Firstly, the senor model of MB-QIS is ...set up. Then global optimal thresholds theory is analyzed and a thresholds optimization algorithm based on the binary search is designed to determine the optimal global thresholds. Finally, the high dynamic range (HDR) images are reconstructed by the noniterative maximum likelihood estimation (MLE) image reconstruction method. The results of simulation prove that HDR imaging of MB-QIS is realized by the proposed method effectively.
In this paper, a method to reduce the effect on image quality caused by the parasitic resistance of column bus in high-resolution cMOS image sensors is presented. Through the mathematical model of ...the column bus, the effect on image quality caused by the resistance is analyzed. The resistance would cause two nonideal factors: dynamic swing reduction and nonlinearity. To reduce the effect of the nonideal factors, this paper utilizes a layout design by putting the readout circuit and column bias circuit on different sides of the pixel array. The relationship among the resistance, light intensity of input, and standard deviation of output gray levels is analyzed. In a 0.13-<inline-formula> <tex-math notation="LaTeX">\mu \text{m} </tex-math></inline-formula> CMOS process and a 12 cm <inline-formula> <tex-math notation="LaTeX">\times </tex-math></inline-formula> 12 cm pixel array, the simulation result shows that the resistance would cause column stripes or gradient under a traditional method. Under the proposed method, the peak standard deviation under uniform illumination decreases from 16.25 to 1.44. The peak signal-to-noise ratio increases from 64.66 to 91.64 dB and the structural similarity index increases from 0.79 to 0.97. The proposed method can enhance image quality for high-resolution image sensors significantly.
This brief presents a 32-stage CMOS time delay integration image sensor with on-chip column parallel analog accumulator. Temporal oversampling technique is applied in the sensor to realize ...synchronous signal capturing. A column parallel analog accumulator with layout size of 0.09 mm 2 is integrated at both sides of pixel array. Through adopting input-offset storing technique, a column fixed pattern noise because of the amplifier's offset variations is reduced by the accumulator. The accumulator also acts as a pixel noise canceller. The fabricated chip in 0.18- μm one-poly four-metal 1.8/3.3-V CMOS technology achieves the maximum line rate of 3875 lines/s. The measured signal-to-noise ratio of the fabricated sensor is improved on average by 11.9 dB at 16 stages and 14.2 dB at 32 stages. The presented sensor is suitable for application in low illumination, high scanning speed, and remote sensing systems.
The full well capacity (FWC) of the four-transistor pixel in CMOS image sensors (CISs) should be a constant which is decided by photodiode structure, doping, and manufacturer, whereas the measured ...FWC in experiments varies with the incident light intensity. In this paper, a model for the light-dependent FWC is developed. The model includes two sources that contribute to the extra light-dependent charge. They are collected along with the intrinsic full well charge in the photodiode or the floating diffusion. The first source comes from the equilibrium between the photocurrent and the photodiode forward current. The other source is the extra collected charges during charge transfer. An analysis model is developed to describe these two light-dependent sources, and the saturated output shows logarithmic and linear relationship with light intensity at low- and high-light condition, respectively. A device level simulation using technology computer aided design software was performed to verify the proposed model. Furthermore, a prototype chip with 15-μm × 15-μm pixels fabricated in a 0.18-μm CIS process was tested. The simulation and measurement results exhibit fairly good consistency with the proposed model. The estimation of the intrinsic FWC is also discussed.
In order to eliminate the fixed-pattern noise (FPN) in the output image of time-delay-integration CMOS image sensor (TDI-CIS), a FPN correction method based on gray value compensation is proposed. ...One hundred images are first captured under uniform illumination. Then, row FPN (RFPN) and column FPN (CFPN) are estimated based on the row-mean vector and column-mean vector of all collected images, respectively. Finally, RFPN are corrected by adding the estimated RFPN gray value to the original gray values of pixels in the corresponding row, and CFPN are corrected by subtracting the estimated CFPN gray value from the original gray values of pixels in the corresponding column. Experimental results based on a 128-stage TDI-CIS show that, after correcting the FPN in the image captured under uniform illumination with the proposed method, the standard-deviation of row-mean vector decreases from 5.6798 to 0.4214 LSB, and the standard-deviation of column-mean vector decreases from 15.2080 to 13.4623 LSB. Both kinds of FPN in the real images captured by TDI-CIS are eliminated effectively with the proposed method.
In this paper, an accumulation technique suitable for digital domain CMOS time delay integration (TDI) image sensors is proposed to reduce power consumption without degrading the rate of imaging. In ...terms of the slight variations of quantization codes among different pixel exposures towards the same object, the pixel array is divided into two groups: one is for coarse quantization of high bits only, and the other one is for fine quantization of low bits. Then, the complete quantization codes are composed of both results from the coarse-and-fine quantization. The equivalent operation comparably reduces the total required bit numbers of the quantization. In the 0.18 µm CMOS process, two versions of 16-stage digital domain CMOS TDI image sensor chains based on a 10-bit successive approximate register (SAR) analog-to-digital converter (ADC), with and without the proposed technique, are designed. The simulation results show that the average power consumption of slices of the two versions are 6 . 47 × 10 - 8 J/line and 7 . 4 × 10 - 8 J/line, respectively. Meanwhile, the linearity of the two versions are 99.74% and 99.99%, respectively.
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