Characterization of near-interface traps (NITs) in commercial SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) is essential because they adversely impact both performance and ...reliability by reducing the channel carrier mobility and causing threshold-voltage drift. In this work, we have applied a newly developed integrated-charge technique to measure the density of NITs that are active in the above-threshold region of commercial SiC MOSFETs. The results demonstrate that NITs trap about 10% of the channel electrons for longer than 500 ns.
We investigate the impact of power MOSFET channel width on the power efficiency of a switch-mode power supply. With this analysis, we derive a circuit-specific criterion that minimizes the power ...dissipated by a power MOSFET, which is based on the ratio between on resistance and output capacitance of the MOSFET and is independent of its technological parameters. The effect of channel width on the power dissipation is illustrated by simulation-based analysis, which also provide an example of a published non-optimum selection of a power MOSFET and demonstrate the advantage of the newly proposed method for MOSFET selection.
Oxide traps existing in 4H-SiC MOS capacitors with fast response times that are active in the strong accumulation and depletion regions were characterized by an integrated-charge method. The method ...is based on the measurement of charging and discharging voltages across MOS capacitors in response to high-frequency voltage pulses. This method can identify traps with response times in the order of hundreds of nanoseconds. The results reveal an increasing density of near-interface traps with energy levels above the bottom of the conduction band, which are the active defects reducing the channel-carrier mobility in 4H-SiC MOSFETs.
Two different equations for the current through voltage-dependent capacitances are used in the literature. One equation is obtained from the time derivative of charge that is considered as ...capacitance-voltage product: <inline-formula> <tex-math notation="LaTeX">{\it dQ/dt=dC(V)V/dt=C(V)dV/dt+VdC(V)/dt.} </tex-math></inline-formula> In the second equation, the term <inline-formula> <tex-math notation="LaTeX">{\it VdC(V)/dt} </tex-math></inline-formula> does not exist: <inline-formula> <tex-math notation="LaTeX">{\it dQ/dt=} {\it C(V)dV/dt} </tex-math></inline-formula>. This paper clears the ongoing confusion caused by the difference between these two equations. We use the voltage-dependent parasitic capacitance of a commercial Schottky diode in reverse bias mode to test experimentally both equations. The result is that it is incorrect to add the term <inline-formula> <tex-math notation="LaTeX">{\it VdC(V)/dt} </tex-math></inline-formula> in the first equation with the measured capacitance. We also perform a theoretical analysis, which shows that the differential capacitance, <inline-formula> <tex-math notation="LaTeX">{\it C(V)=dQ/dV} </tex-math></inline-formula>, in the correct current equation corresponds to the physical parameters of the diode capacitance.
Analysis of the switching losses in a power MOSFET is crucial for the design of efficient power electronic systems. Currently, the state-of-the-art technique is based on measured drain current and ...drain-to-source voltage during the switching intervals. However, this technique does not separate the switching power due to the resistance of the MOSFET channel and due to the parasitic capacitances. In this paper, we propose a measurement method to extract the power dissipation due to the parasitic capacitances of a MOSFET, providing useful information for device selection and for the design of efficient power electronic systems. The proposed method is demonstrated on a basic boost converter. The proposed method shows that the existing method underestimates the turn-On losses by 41% and overestimates the turn-Off losses by 35%.
This brief presents direct electrical measurement of active defects in the strong-accumulation region of N-type 4H-SiC MOS capacitors, which corresponds to the strong-inversion region of N-channel ...MOSFETs. The results demonstrate the existence of an active defect in the gate oxide, located very close to the SiC surface, with localized energy levels between 0.13 eV and 0.23 eV above the bottom of the conduction band. The observed spatial and energy localizations indicates that this is a well-defined defect.
Abstract This article investigates the trapping mechanism in AlGaN/GaN heterostructure. For our study, the traps within the AlGaN layer are introduced at the interface and near the interface of ...AlGaN/GaN, in the SILVACO TCAD tool. Frequency-dependent capacitance-Voltage ( CVF ) curves are obtained to study the impact of traps on device performance. From the CVF curve, it is found that the existence of interface traps introduces a shift in capacitance along the gate voltage axis. These traps introduce the threshold voltage ( V TH ) shift. Furthermore, a detailed study of near-interface traps (NITs) is done based on tunneling mechanisms. For our investigation, the NITs are positioned at 0.5 nm, 1 nm, and 1.5 nm away from the AlGaN/GaN interface. The response of the NITs reduces the capacitance value in the accumulation region. The response of the NITs is explained through the capacitance charge model and border trap model. For NITs placed 0.5 nm away from the interface, the frequency dispersion in the accumulation region becomes evident. On the contrary, the dispersion reduces significantly, as the NITs goes deeper upto 1.5 nm. The results indicate that the NITs nearer to the interface respond to high frequencies. Further, the temperature dependent capacitance–voltage analysis is done for both interface and NITs, to understand the effect of temperature on frequency dispersion.
The suboptimal performance and low channel-carrier mobility of silicon carbide (SiC) power MOSFETs are attributed to a high density of oxide traps near the 4H-SiC/SiO<inline-formula> <tex-math ...notation="LaTeX">_{\text{2}}</tex-math> </inline-formula> interface. In this article, a commercial 1200-V SiC trench MOSFET has been compared with a planar MOSFET obtained from the same manufacturer. We employed a newly developed integrated-charge method to quantify the near-interface traps (NITs). The results reveal that, at operating gate voltages, 15% of the total channel electrons were trapped for longer than 500 ns in the planar MOSFET compared to 9% in the trench MOSFET.
Transistor-based on Gallium Nitride (GaN) technology, has enabled energy-saving power electronics to alleviate global energy utilization. Being the initial stages of the development as compared to ...mature Silicon (Si) technology, the critical issues related to the reliability of GaN-based devices are not much explored. To better understand the device reliability, the article reviews and summarizes, the trapping induced threshold voltage (VTH) instability and dynamic ON-resistance (RDS,ON) degradation specifically, for normally-off p-GaN gate HEMTs in power applications. The variation in threshold voltage and dynamic ON-resistance is examined for different operating regimes, which include biasing voltage and temperature. Furthermore, the characterization methods and test setups are discussed in detail to extract the true value of RDS,ON observed in the GaN power converter. Various models and techniques are reviewed as well which improves the converter conduction losses, introduced by dynamic ON-resistance. Additionally, different techniques are discussed in the review to control the VTH instability. It is observed that the point and extended defects created during device fabrication or charge trapping in GaN buffer, AlGaN layer, surface, or at their interface, induce variation in (VTH) and RDS,ON, for both the gate and drain stress regimes. Threshold voltage stability is mainly affected by the traps below the gate region, while the traps across the gate to drain access region influence the RDS,ON. The variation in RDS,ON value, is seen to be dependent on stress time, different device technology, and, switching conditions (frequency and duty cycle). In power application, the dynamic resistance shows a more pronounced effect on converter efficiency as compared to the VTH.
•The article addresses the reliability issues in p-GaN Power HEMTs.•Mainly the trapping-induced VTH instability and RDS, ON degradation are considered.•Various characterization method and test-setup are discussed to extract RDS, ON value.•Methods to control RDS, ON degradation and VTH instability are studied.
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