The development of micro-scale mechanical systems has been moving rapidly, allowing an opportunity to the semiconductor detectors to have ever more power located on the active region. Miniaturization ...associated with micro-channel technologies allows the design of micro-system structures that are able to cool silicon pixel detectors with power of the order of some W/cm
2 with thickness less than 0.3% of radiation length. We present the design and thermo-hydraulic test results for low material budget support and cooling obtained through
forced liquid convection in micro-channels, developed for the innermost layer (Layer 0) of SuperB silicon vertex tracker.
Pixel detectors at future colliders will need to match very stringent requirement on position resolution. To ensure the needed mechanical stability and the removal of the power dissipated by the ...read-out electronic, the support structure and cooling add an important contribution to the total material in the active area, in terms of radiation length. We present the development, the construction and the mechanical–thermal characterization of prototypes of light material support for pixel detectors with microchannel for heat evacuation through forced convection of liquid coolant.
The solution we choose shows several advantages: heat exchange is taking place efficiently due to the high ratio surface/volume and so high thermal conductivities can be obtained, minimally affecting the stiffness of the structure; the thermal resistances are reduced because of the contiguity between the fluid and the circuit dissipating power; the uniformity of temperature on the surface covered by of the sensors is also kept under control. Several prototypes implementing different geometries of micro-machined channels have been realized in composites materials (CFRP). FEA studies have been performed to validated the experimental test conducted in the thermo-fluid dynamic test bench we recently assembled in the INFN Pisa laboratory.
In the design of the Silicon Vertex Tracker for the high luminosity SuperB collider, very challenging requirements are set by physics and background conditions on its innermost Layer0: small radius ...(about 1.5cm), resolution of 10–15μm in both coordinates, low material budget <1%X0, and the ability to withstand a background hit rate of several tens of MHz/cm2. Thanks to an intense R&D program the development of Deep NWell CMOS MAPS (with the ST Microelectronics 130nm process) has reached a good level of maturity and allowed for the first time the implementation of thin CMOS sensors with similar functionalities as in hybrid pixels, such as pixel-level sparsification and fast time stamping. Further MAPS performance improvements are currently under investigation with two different approaches: the INMAPS CMOS process, featuring a quadruple well and a high resistivity substrate, and 3D CMOS MAPS, realized with vertical integration technology. In both cases specific features of the processes chosen can improve charge collection efficiency, with respect to a standard DNW MAPS design, and allow to implement a more complex in-pixel logic in order to develop a faster readout architecture. Prototypes of MAPS matrix, suitable for application in the SuperB Layer0, have been realized with the INMAPS 180nm process and the 130nm Chartered/Tezzaron 3D process and results of their characterization will be presented in this paper.
The front-end chip of the SuperB SVT detector Giorgi, F.; Comotti, D.; Manghisoni, M. ...
Nuclear instruments & methods in physics research. Section A, Accelerators, spectrometers, detectors and associated equipment,
08/2013, Letnik:
718
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The asymmetric e+e− collider SuperB is designed to deliver a high luminosity, greater than 1036cm−2s−1, with moderate beam currents and a reduced center of mass boost with respect to earlier ...B-Factories. The innermost detector is the Silicon Vertex Tracker which is made of 5 layers of double sided silicon strip sensors plus a layer 0, that can be equipped with short striplets detectors in a first phase of the experiment. In order to achieve an overall track reconstruction efficiency above 98% it is crucial to optimize both analog and digital readout circuits. The readout architecture being developed for the front-end chips will be able to cope with the very high rates expected in the first layer. The digital readout will be optimized to be fully efficient for hit rates up to 2MHz/strip, including large margins on the maximum expected background rates, but can potentially accommodate higher rates with a proper tuning of the buffer depth. The readout is based on a triggered architecture where each of the 128 strip channel is provided with a dedicated digital buffer. Each buffer collects the digitized charge information by means of a 4-bit TOT, storing it in conjunction with the related time stamp. The depth of buffers was dimensioned considering the expected trigger latency and hit rate including suitable safety margins. Every buffer is connected to a highly parallelized circuit handling the trigger logic, rejecting expired data in the buffers and channeling the parallel stream of triggered hits to the common output of the chip. The presented architecture has been modeled by HDL language and investigated with a Monte Carlo hit generator emulating the analog front-end behavior. The simulations showed that even applying the highest stressing conditions, about 2MHz per strip, the efficiency of the digital readout remained above 99.8%.
Beam test results for the SuperB-SVT thin striplet detector Fabbri, L.; Comotti, D.; Manghisoni, M. ...
Nuclear instruments & methods in physics research. Section A, Accelerators, spectrometers, detectors and associated equipment,
08/2013, Letnik:
718
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The baseline detector option for the first layer of the SuperB Silicon Vertex Tracker (SVT) is a high resistivity double-sided silicon device with short strips (striplets) at 45° angle to the ...detector's edge. A prototype was tested with a 120GeV/c pion beam in September 2011 at the SPS-H6 test-beam line at CERN. In this paper studies on efficiency, resolution and cluster size are reported.
Physics and high background conditions set very challenging requirements on readout speed, material budget and resolution for the innermost layer of the SuperB Silicon Vertex Tracker operated at the ...full luminosity. Monolithic Active Pixel Sensors (MAPS) are very appealing in this application since the thin sensitive region allows grinding the substrate to tens of microns. Deep N-Well MAPS, developed in the ST 130nm CMOS technology, achieved in-pixel sparsification and fast time stamping. Further improvements are being explored with an intense R&D program, including both vertical integration and 2D MAPS with the INMAPS quadruple well. We present the results of the characterization with IR laser, radioactive sources and beam of several chips produced with the 3D (Chartered/Tezzaron) process. We have also studied prototypes exploiting the features of the quadruple well and the high resistivity epitaxial layer of the INMAPS 180nm process. Promising results from an irradiation campaign with neutrons on small matrices and other test-structures, as well as the response of the sensors to high energy charged tracks are presented.
The latest advances in the design and characterization of several pixel sensors developed to satisfy the very demanding requirements of the innermost layer of the SuperB Silicon Vertex Tracker will ...be presented in this paper. The SuperB machine is an electron positron collider operating at the ϒ(4S) peak to be built in the very near future by the Cabibbo Lab consortium. A pixel detector based on extremely thin, radiation hard devices able to cope with rate in the tens of MHz/cm2 range will be the optimal solution for the upgrade of the inner layer of the SuperB tracking system. At present several options with different levels of maturity are being investigated to understand advantages and potential issues of the different technologies: thin hybrid pixels, Deep N-Well CMOS MAPS, INMAPS CMOS MAPS featuring a quadruple well and high resistivity substrates and CMOS MAPS realized with Vertical Integration technology. The newest results from beam test, the outcomes of the radiation damage studies and the laboratory characterization of the latest prototypes will be reported.
Autoaggression to retard senility PETRAGNANI, G
Atti della Accademia dei fisiocritici in Siena. Sezione medico-fisica,
1953, Letnik:
21
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