The Fast TracKer (FTK) is an ATLAS trigger upgrade built for full-event, low-latency, high-rate tracking. The FTK core, made of 9U VME boards, performs the most demanding computational task. The ...associative memory board (AMB) serial link processor and the auxiliary card (AUX), plugged on the front and back sides of the same VME slot, constitute the processing unit (PU), which finds tracks using hits from eight layers of the inner detector. The PU works in pipeline with the second stage board (SSB), which finds 12-layer tracks by adding extra hits to the identified tracks. In the designed configuration, 16 PUs and four SSBs are installed in a VME crate. The high power consumption of the AMB, AUX, and SSB (respectively, of about 250, 70, and 160 W per board) required the development of a custom cooling system. Even though the expected power consumption for each VME crate of the FTK system is high compared with a common VME setup, the 8 FTK core crates will use ≈60 kW, which is just a fraction of the power and the space needed for a CPU farm performing the same task. We report on the integration of 32 PUs and eight SSBs inside the FTK system, on the infrastructures needed to run and cool them, and on the tests performed to verify the system processing rate and the temperature stability at a safe value.
The design and experimental demonstration of a 16-channel frequency-domain multiplexing (FDM) read-out for transition-edge sensor bolometers is presented. This MUX electronics is intended to read out ...the 326 spiderweb bolometers of the LSPE/SWIPE balloon-borne experiment, which aims at the detection of the B mode polarization of the cosmic microwave background at large angular scales. The cryogenic part of our 16-channel FDM read-out chain features LC resonators composed of custom Nb superconducting inductors and surface mount device ceramic capacitors mounted on boards next to the detector wafers, at 300 mK, while the superconducting quantum interference device board is at 1.6 K. The warm section is based on a modular solution, with mezzanine plug-ins for digital-to-analog converters, analog-to-digital converters and a system-on-chip (based on the Altera Cyclone V field programmable gate array). The warm electronics handles the generation of the FDM tones, the de-multiplexing and the digital signal analysis including, e.g. cosmic ray glitches removal. Here, we recall its specifications, we address noise considerations, and finally we present the latest results obtained using flight models of our custom-designed boards.
Abstract
The fast reconstruction of charged particle tracks with high efficiency and track quality is an essential part of the online data selection for the ATLAS experiment at the High Luminosity ...LHC.
Dedicated custom designed hardware boards and software simulations have been developed to assess the feasibility of a Hardware Tracking Trigger (HTT) system.
The Pattern Recognition Mezzanine (PRM), as part of the HTT system, has been designed to recognize track candidates in silicon detectors with Associative Memory ASICs and to select and reconstruct tracks using linearized algorithms implemented in an Intel Stratix 10 MX FPGA.
The highly parallelized FPGA design makes extensive use of the integrated High-Bandwidth-Memory.
In this paper, the FPGA design for the PRM board is presented. Its functionalities have been verified in both simulations and hardware tests on an Intel Stratix 10 MX development kit.
As the LHC luminosity is ramped up to 3 × 10 34 cm 2 s 1 and beyond, the high rates, multiplicities, and energies of particles seen by the detectors will pose a unique challenge. Only a tiny fraction ...of the produced collisions can be stored offline and immense real-time data reduction is needed. An effective trigger system must maintain high trigger efficiencies for the physics we are most interested in while suppressing the enormous QCD backgrounds. This requires massive computing power to minimize the online execution time of complex algorithms. A multi-level trigger is an effective solution to meet this challenge. The Fast Tracker (FTK) is an upgrade to the current ATLAS trigger system that will operate at full Level-1 output rates and provide high-quality tracks reconstructed over the entire inner detector by the start of processing in the Level-2 Trigger. FTK solves the combinatorial challenge inherent to tracking by exploiting the massive parallelism of associative memories that can compare inner detector hits to millions of pre-calculated patterns simultaneously. The tracking problem within matched patterns is further simplified by using pre-computed linearized fitting constants and relying on fast DSPs in modern commercial FPGAs. Overall, FTK is able to compute the helix parameters for all tracks in an event and apply quality cuts in less than 100 μs. The system design is defined and the performance presented with respect to high transverse momentum (high-p T ) Level-2 objects: b jets, tau jets, and isolated leptons. We test FTK algorithms using the full ATLAS simulation with WH events up to 3 × 10 34 cm 2 s 1 luminosity and compare the FTK results with the offline tracking capability. We present the architecture and the reconstruction performance for the mentioned high-p T Level-2 objects.
A high-performance "pattern matching" implementation based on the Associative Memory (AM) system is presented. It is designed to solve the real-time hit-to-track association problem for particles ...produced in high-energy physics experiments at hadron colliders. The processing time of pattern recognition in CPU-based algorithms increases rapidly with the detector occupancy due to the limited computing power and input-output capacity of hardware available on the market. The AM system presented here solves the problem by being able to process even the most complex hadron collider events produced at a rate of 100 kHz with an average latency smaller than 10 μs. The board built for this goal is able to execute ~12 petabyte comparisons per second, with peak power consumption below 250 W, uniformly distributed on the large area of the board.
We present critical temperature measurements of titanium thin films annealed in an argon atmosphere at various temperatures. We are able to depress the TC by up to 200 mK from an initial TC of 540 mK ...by increasing the temperature at which the films are post-annealed from 80 to 275 ∘C. We find an anti-correlation trend between the annealing temperature and the measured TC. We also briefly discuss how we plan to use these films to produce TES detectors to be used in the LSPE/SWIPE balloon-borne cosmic microwave background polarimeter, which is slated to launch in December 2019.
The associative memory (AM) system of fast tracker (FTK) processor has been designed for the tracking trigger upgrade to the ATLAS detector at the Conseil Europeen Pour La Recherche Nucleaire large ...hadron collider. The system performs pattern matching (PM) using the detector hits of particles in the ATLAS silicon tracker. The AM system is the main processing element of FTK and is mainly based on the use of application-specified integrated circuits (ASICs) (AM chips) designed to execute PM with a high degree of parallelism. It finds track candidates at low resolution which become seeds for a full resolution track fitting. The AM system implementation is based on a collection of large 9U Versa Module Europa (VME) boards, named "serial link processors" (AMBSLPs). On these boards, a huge traffic of data is implemented on a network of 900 2-Gb/s serial links. The complete AM-based processor consumes much less power (~50 kW) than its CPU equivalent and its size is much smaller. The AMBSLP has a power consumption of ~250 W and there will be 16 of them in a crate. This results in unusually large power consumption for a VME crate and the need for complex custom infrastructure in order to have sufficient cooling. This paper reports on the design and testing of the infrastructures needed to run and cool the system which will include 16 AMBSLPs in the same crate, the integration of the AMBSLP inside a first FTK slice, the performance of the produced prototypes (both hardware and firmware), as well as their tests in the global FTK integration. This is an important milestone to be satisfied before the FTK production.
The use of tracking information at the trigger level in the LHC Run II period is crucial for the trigger and data acquisition system and will be even more so as contemporary collisions that occur at ...every bunch crossing will increase in Run III. The Fast TracKer is part of the ATLAS trigger upgrade project; it is a hardware processor that will provide every Level-1 accepted event (100 kHz) and within 100mus, full tracking information for tracks with momentum as low as 1 GeV . Providing fast, extensive access to tracking information, with resolution comparable to the offline reconstruction, FTK will help in precise detection of the primary and secondary vertices to ensure robust selections and improve the trigger performance.
The authors describe a VLSI processor for pattern recognition based on content addressable memory (CAM) architecture, optimized for on-line track finding in high-energy physics experiments. A large ...CAM bank stores all trajectories of interest and extracts the ones compatible with a given event. This task is naturally parallelized by a CAM architecture able to output identified trajectories, searching for matches on 96-bit wide patterns, in just a few 40-MHz clock cycles. We have developed this device (called the AMchip03 processor) for the silicon vertex trigger (SVT) upgrade at the Collider Detector experiment at Fermilab (CDF) using a standard-cell VLSI design methodology. This approach provides excellent pattern density, while sparing many of the complexities and risks associated to a full-custom design. The cost/performance ratio is better by well more than one order of magnitude than an FPGA-based design. This processor has a flexible and easily configurable structure that makes it suitable for applications in other experimental environments. They look forward to sharing this technology
Thin pixel development for the SuperB silicon vertex tracker Rizzo, G.; Avanzini, C.; Batignani, G. ...
Nuclear instruments & methods in physics research. Section A, Accelerators, spectrometers, detectors and associated equipment,
09/2011, Letnik:
650, Številka:
1
Journal Article
Recenzirano
The high luminosity SuperB asymmetric
e
+
e
−
collider, to be built near the INFN National Frascati Laboratory in Italy, has been designed to deliver a luminosity greater than 10
36
cm
−2
s
−1 with ...moderate beam currents and a reduced center of mass boost with respect to earlier B-Factories. An improved vertex resolution is required for precise time-dependent measurements and the SuperB Silicon Vertex Tracker will be equipped with an innermost layer of small radius (about 1.5
cm), resolution of
10
–
15
μ
m
in both coordinates, low material budget (
<
1
%
X0), and able to withstand a background rate of several tens of MHz/cm
2. The ambitious goal of designing a thin pixel device with these stringent requirements is being pursued with specific R&D programs on different technologies: hybrid pixels, CMOS MAPS and pixel sensors developed with vertical integration technology. The latest results on the various pixel options for the SuperB SVT will be presented.
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