A spark-resistant bulk-micromegas chamber for high-rate applications Alexopoulos, T.; Burnens, J.; de Oliveira, R. ...
Nuclear instruments & methods in physics research. Section A, Accelerators, spectrometers, detectors and associated equipment,
06/2011, Letnik:
640, Številka:
1
Journal Article
Recenzirano
Odprti dostop
We report on the design and performance of a spark-resistant bulk-micromegas chamber. The principle of this design lends itself to the construction of large-area muon chambers for the upgrade of the ...detectors at the Large Hadron Collider at CERN for luminosities in excess of 10
34
cm
−2
s
−1 or other high-rate applications.
The address in real-time data driver card (ADDC) is designed to transmit the trigger data in the micromesh gaseous structure (Micromegas, MM) detector of the ATLAS new small wheel (NSW) upgrade. The ...address in real-time (ART) signals are generated by the front-end application-specific integrated circuit (ASIC), named VMM chip, to indicate the address of the first above-threshold event. A custom ASIC (ART ASIC) is designed to receive the ART signals from the VMM chip and implement the hit selection. The processed data from the ART ASIC will be transmitted out of the NSW through the gigabit transceiver (GBTx) serializer, the unidirectional versatile twin transmitter (VTTx), and fiber-optic links. The ART signal is critical for the ATLAS experiment trigger selection; thus, the performance and stability of the ADDC is very important. To ensure extensive testing of the ADDC, a field-programmable gate array (FPGA) mezzanine card (FMC)-based testing platform and a specially designed firmware/software are developed. This test platform works with the commercial Xilinx VC707 FPGA development kit; independent of the other electronics in the NSW, it can test all the functions of the ADDC and it has long-term stability. This article will introduce the design, testing procedure, and results of the ADDC and the FMC testing platform.
The VMM readout system Alexopoulos, T.; Antrim, D.; Bakalis, C. ...
Nuclear instruments & methods in physics research. Section A, Accelerators, spectrometers, detectors and associated equipment,
03/2020, Letnik:
955, Številka:
C
Journal Article
Recenzirano
Odprti dostop
The New Small Wheel Upgrade of the ATLAS experiment at CERN, planned to take place at 2020, requires a new generation of front-end electronics that will support its data acquisition requirements. The ...VMM Application-Specific Integrated Circuit has been in development for the last seven years to serve as the foundation of the New Small Wheel’s readout scheme. It has gone through three major revisions and a minor one, the latter being the production version. To facilitate the testing and readout of the VMM, as well as to study its detector performance, a complete readout system has been developed. It consists of flexible Field-Programmable Gate Array logic with extensive functionality, and an efficient software framework providing the user interface. This system, referred to as the ”The VMM Readout System”, has been used in test-beam campaigns at CERN, as well as in bench calibration and testing measurement scenarios for the past several years, supporting all readout modes and features of the VMM.
Abstract
The Large Hadron Collider (LHC) at CERN will perform a series of upgrades to allow luminosity increases during the next physics runs expected from 2022 on. These will also significantly ...increase the trigger rates of all the detectors. As part of the ATLAS Phase-I upgrade, the current Small Wheel muon detectors will be replaced with state-of-the-art New Small Wheel (NSW) detectors to cope with the increased luminosity of the LHC. The Address in Real Time Data Driver Card (ADDC) is designed to transmit the trigger data from the resistive Micro-Mesh Gaseous Structure (Micromegas) detectors of the NSW. The ART ASIC on the ADDC is a custom-designed chip to receive the Address in Real Time (ART) signals from the VMM front-end ASIC and perform hit-selection processing. The processed trigger data is then sent to the Trigger Processor (TP) through optical links. A total of 512 ADDCs will be installed on the detector close to the front-end boards. Therefore, those cards must be able to work properly in a high radiation and magnetic field environment. After four rounds of prototyping, the ADDC production was launched in January of 2019. 600 ADDC boards have been produced and tested with an automated test stand. This test setup can simulate the front-end signals and provide "Level-1 Data Driver Card" (L1DDC) functions as well as part of the TP functions. Thus, the ADDC functionality and stability can be verified without the remaining NSW electronics. This paper describes the ADDC hardware prototype development, radiation and integration testing, and the ADDC automated production test procedure.
Abstract
The foreseen upgrades of the Large Hadron Collider (LHC) are expected to increase the required throughput of the front-end and back-end electronics that support the readout of the LHC ...detectors. Therefore, the complexity of the electronics systems will be increased as well. An example of this is the electronics system of the New Small Wheel (NSW) upgrade of the ATLAS detector, which will be comprised of a number of Field-Programmable Gate Arrays (FPGAs), and Application-Specific Integrated Circuits (ASICs). These ASICs will be configured and monitored by the Slow Control Adapter (SCA), another ASIC designed for this purpose. The Slow Control Adapter eXtension (SCAX) on the other hand, is an FPGA module designed to support FPGA systems that are part of the ATLAS electronics scheme by reading and writing their configuration parameters and status indicators. SCAX emulates both the I2C interface of the SCA used to access the NSW ASICs, as well as the communication protocol implemented between the SCA and the back-end infrastructure. It thereby enables using the same OPC-UA server and back-end software suite that support the ASICs, to also interface with the FPGAs that are part of the same system. This work describes the context of the SCAX's implementation, alongside architectural considerations of the module, features, and techniques to validate its hardware implementation across a variety of FPGA devices.
Identification of circles from datapoints using the Legendre transform Alexopoulos, T.; Iakovidis, G.; Leontsinis, S. ...
Nuclear instruments & methods in physics research. Section A, Accelerators, spectrometers, detectors and associated equipment,
05/2014, Letnik:
745
Journal Article
Recenzirano
In this paper we present a method of reconstructing the circle parameters from a set of datapoints on a plane. The method is based on the geometrical Legendre transform. We test the method under ...various scenarios using Monte Carlo generated data. These scenarios include variation of the noise hits percentage, uncertainties in the hit position and the number of datapoints. The technique is proven to be robust and provide quickly and efficiently very accurate results. Furthermore, the use of the geometrical Legendre transform method for the identification of two overlapping circles is shown.
The ART Data Driver Card (ADDC) will be used in the ATLAS muon upgrade to process and transmit the Address in Real Time (ART) signals, which are generated by the front end chip (VMM) to indicate the ...location of the first above-threshold event. This ART signal is encoded to represent the address of the first threshold-crossing strip for trigger processing and the magnitude information is not included. The ADDC will be installed on the detector with high radiation and magnetic field thus a custom ASIC (ART ASIC) will be used to receive the ART signals from VMM and do the hit-selection processing. Processed data from ART ASIC will be transmitted out of the detector to the trigger processor through fiber connection. To evaluate the performance of the ADDC before the ART ASIC is produced, an FPGA based prototype was built. This prototype includes most of the major components of the ADDC, while a Xilinx Artix-7 FPGA is used to emulate the ART ASIC. The bench test and integration test results of this prototype will also be described.
The spatial resolution of a detector, using a reference detector telecscope, can be measured applying the geometric mean method, with tracks reconstructed from hits of all the detectors, including ...(sigma sub(in)) and excluding (sigma sub(ex)) the hit from the detector under study. The geometric mean of the two measured resolution values (sigma = radicalsigma sub(ex)sigma sub(in)), is proposed to provide a more accurate estimate of the intrinsic detector resolution. This method has been tested using a Monte Carlo algorithm and is proven to give accurate results, independently of the distance between the detectors used for the track fitting. The method does not give meaningful results if all the detectors do not carry the same characteristics.
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