This invited talk will present recent highlights from our research on two-dimensional (2D) materials including graphene, boron nitride (h-BN), and transition metal dichalcogenides (TMDs). The results ...span from fundamental measurements and simulations, to device- and several unusual system-oriented applications which take advantage of unique 2D material properties. Basic electrical, thermal, and thermoelectric properties of 2D materials will also be discussed.
Scalable fabrication of high quality photodetectors derived from synthetically grown monolayer transition metal dichalcogenides is highly desired and important for wide range of nanophotonics ...applications. We present here scalable fabrication of monolayer MoS2 photodetectors on sapphire substrates through an efficient process, which includes growing large scale monolayer MoS2 via chemical vapor deposition (CVD), and multi-step optical lithography for device patterning and high quality metal electrodes fabrication. In every measured device, we observed the following universal features: (i) negligible dark current \((I_{dark}\leqslant10 fA)\); (ii) sharp peaks in photocurrent at \(\sim\)1.9eV and \(\sim\)2.1eV attributable to the optical transitions due to band edge excitons; (iii) a rapid onset of photocurrent above \(\sim\)2.5eV peaked at \(\sim\)2.9eV due to an excitonic absorption originating from the van Hove singularity of MoS\(_2\). We observe low (\(\leqslant 300\%\)) device-to-device variation of photoresponsivity. Furthermore, we observe very fast rise time \(\sim\)0.5 ms, which is three orders of magnitude faster than other reported CVD grown 1L-MoS\(_2\) based photodetectors. The combination of scalable device fabrication, ultra-high sensitivity and high speed offer a great potential for applications in photonics.
Copper interconnects in modern integrated circuits require ultra-thin barriers to prevent intermixing of Cu with surrounding dielectric materials. Conventional barriers rely on metals like TaN, ...however their finite thickness reduces the cross-sectional area and significantly increases the resistivity of nanoscale interconnects. In this study, a new class of two-dimensional (2D) Cu diffusion barriers, hexagonal boron nitride (h-BN) and molybdenum disulfide (MoS2), is demonstrated for the first time. Using time-dependent dielectric breakdown measurements and scanning transmission electron microscopy coupled with energy dispersive X-ray spectroscopy and electron energy loss spectroscopy, these 2D materials are shown to be promising barrier solutions for ultra-scaled interconnect technology. The predicted lifetime of devices with directly deposited 2D barriers can achieve three orders of magnitude improvement compared to control devices without barriers.
The operation of resistive and phase-change memory (RRAM and PCM) is controlled by highly localized self-heating effects, yet detailed studies of their temperature are rare due to challenges of ...nanoscale thermometry. Here we show that the combination of Raman thermometry and scanning thermal microscopy (SThM) can enable such measurements with high spatial resolution. We report temperature-dependent Raman spectra of HfO\(_2\), TiO\(_2\) and Ge\(_2\)Sb\(_2\)Te\(_5\) (GST) films, and demonstrate direct measurements of temperature profiles in lateral PCM devices. Our measurements reveal that electrical and thermal interfaces dominate the operation of such devices, uncovering a thermal boundary resistance of 30 m\(^2\)K\(^{-1}\)GW\(^{-1}\) at GST-SiO\(_2\) interfaces and an effective thermopower 350 \(\mu\)V/K at GST-Pt interfaces. We also discuss possible pathways to apply Raman thermometry and SThM techniques to nanoscale and vertical resistive memory devices.
Emerging applications require computing platforms to extract task-relevant information from increasingly large amounts of data. These requirements place stringent constraints on energy efficiency, ...throughput, latency, and for certain data types, security and privacy of computing platforms. Traditionally, silicon CMOS scaling has been relied upon to meet these energy and delay constraints. However, the energy and delay benefits achievable via scaling are diminishing. Increased vulnerability to various sources of variations (e.g., process, voltage) further exacerbates these energy and speed challenges.
Conventional CMOS scaling and the Moore's law have been the cornerstone of progress in computing hardware technology. However, with dimensional scaling expected to end soon, there is a pressing need ...to find the next information processing hardware that can continue to support the technology revolution. Will this hardware solution be an enhanced or an augmented version of MOSFET or a switch based on a radically new switching mechanism. Ultimately, do we require a complete deviation from the Boolean paradigm itself? In this invited paper, we will review some of the actively pursued future logic, merged logic-memory and related concepts. While it remains unclear which of these options will eventually make it into commercial products, we will argue- based on lessons learnt from the past two decades of transistor development- that sustained and systematic research with careful benchmarking from future workload and applications viewpoint remains the key to success in the quest for the new information processing hardware.
Understanding the thermal properties of two-dimensional (2D) materials and devices is essential for thermal management of 2D applications. Here we perform molecular dynamics simulations to evaluate ...both the specific heat of \(MoS_{2}\) as well as the thermal boundary conductance (TBC) between one to five layers of \(MoS_{2}\) with amorphous \(SiO_{2}\) and between single-layer \(MoS_{2}\) and crystalline \(AlN\). The results of all calculations are compared to existing experimental data. In general, the TBC of such 2D interfaces is low, below ~20 \(MWm^{-2}K^{-1}\), due to the weak van der Waals (vdW) coupling and mismatch of phonon density of states (PDOS) between materials. However, the TBC increases with vdW coupling strength, with temperature, and with the number of \(MoS_{2}\) layers (which introduce additional phonon modes). These findings suggest that the TBC of 2D materials is tunable by modulating their interface interaction, the number of layers, and finding a PDOS-matched substrate, with important implications for future energy-efficient 2D electronics, photonics, and thermoelectrics.
ACS Applied Materials & Interfaces (2017) The electrical and thermal behavior of nanoscale devices based on
two-dimensional (2D) materials is often limited by their contacts and
interfaces. Here we ...report the temperature-dependent thermal boundary
conductance (TBC) of monolayer MoS$_2$ with AlN and SiO$_2$, using Raman
thermometry with laser-induced heating. The temperature-dependent optical
absorption of the 2D material is crucial in such experiments, which we
characterize here for the first time above room temperature. We obtain TBC ~ 15
MWm$^-$$^2$K$^-$$^1$ near room temperature, increasing as ~ T$^0$$^.$$^6$$^5$
in the range 300 - 600 K. The similar TBC of MoS$_2$ with the two substrates
indicates that MoS$_2$ is the "softer" material with weaker phonon irradiance,
and the relatively low TBC signifies that such interfaces present a key
bottleneck in energy dissipation from 2D devices. Our approach is needed to
correctly perform Raman thermometry of 2D materials, and our findings are key
for understanding energy coupling at the nanoscale.
Heat transfer across interfaces of graphene and polar dielectrics (e.g. SiO2) could be mediated by direct phonon coupling, as well as electronic coupling with remote interfacial phonons (RIPs). To ...understand the relative contribution of each component, we develop a new pump-probe technique, called voltage-modulated thermoreflectance (VMTR), to accurately measure the change of interfacial thermal conductance under an electrostatic field. We employed VMTR on top gates of graphene field-effect transistors and find that the thermal conductance of SiO2/graphene/SiO2 interfaces increases by up to {\Delta}G=0.8 MW m-2 K-1 under electrostatic fields of <0.2 V nm-1 . We propose two possible explanations for the observed {\Delta}G. First, since the applied electrostatic field induces charge carriers in graphene, our VMTR measurements could originate from heat transfer between the charge carriers in graphene and RIPs in SiO2. Second, the increase in heat conduction could be caused by better conformity of graphene interfaces un-der electrostatic pressure exerted by the induced charge carriers. Regardless of the origins of the observed {\Delta}G, our VMTR measurements establish an upper limit for heat transfer from unbiased graphene to SiO2 substrates via RIP scattering; i.e., only <2 % of the interfacial heat transport is facilitated by RIP scattering even at a carrier concentration of 4x10^12 cm-2.
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