Using a recently developed gate-sensing and channel- sensing (GSCS) transient analysis method, we have studied the detailed charge-trapping behavior for SONOS-type devices. By adding gate sensing to ...the conventional channel sensing, the two variables (total charge Q tot and mean vertical location x circ) can be solved simultaneously. By using this powerful new tool on several SONOS-type structures, we have studied the charge centroid as well as the capture efficiency of various SONOS devices. Our results clearly prove that electrons are mainly distributed inside the bulk nitride instead of the interfaces between oxide and nitride. For the first time, we show that nitride 7 nm or thicker can essentially capture electrons with 100% efficiency up to a density of Q tot ~10 13 cm -2 . Structures without top blocking oxide suffer from hole back tunneling and show apparent low electron capture efficiency, which led to confusion in the past. Moreover, multilayer stacks of nitride-trapping layers do not provide more efficient interfacial traps.
The physical model for field enhancement (FE) and the edge effects of body-tied FinFET charge-trapping NAND Flash devices are extensively studied in this paper. First, analytical equations are ...derived to provide insight to the FE effect for FinFET devices, and these analytical results are validated by 3-D TCAD simulation and experimental verification. Next, complicated programming and erasing characteristics and transconductance and subthreshold slope ( gm / SS ) behaviors are completely explained by the nonuniform injection behavior along various corner edges in FinFET. FE allows high program and erase speed and larger memory window. On the other hand, the edge effect complicates the device DC I - V , as well as programming and erasing characteristics, and these must be taken into account in memory circuit design.
The band-to-band tunneling hot-electron (BBHE) programming characteristics of the 2 bit/cell p-channel bandgap-engineered silicon-oxide-nitride-oxide-semiconductor (SONOS) (H. T. Lue, et al., in IEDM ...Tech. Diag., p. 331) device are extensively studied. The lateral BBHE profile is extracted by fitting the experimental current-voltage (I-V) characteristics with 2-D simulation. The results suggest that, after BBHE injection, the local channel potential barrier is reduced, which, in turn, raises the Vt of the p-channel device. The 2 bit/cell operation methods and second-bit effect (2 bit interaction) are examined. The effects of channel-length scaling, junction profile, and effective oxide thickness of the gate stack are also addressed
A body-tied FinFET bandgap engineered (BE)-silicon-oxide-nitride-oxide-silicon (SONOS) nand Flash device is successfully demonstrated for the first time. BE-SONOS device with a BE oxide-nitride-oxide ...barrier is integrated in the FinFET structure with a 30-nm fin width. FinFET BE-SONOS can overcome the unsolvable tradeoff between retention and erase speed of the conventional SONOS. Compared with the current floating-gate Flash devices, FinFET BE-SONOS provides both retention and erase-speed performance, while eliminating the scaling limitations and is, thus, an important candidate for further scaling of nand Flash
A complementary metal oxide semiconductor (CMOS)-compatible WO x based resistive memory has been developed. The WO x memory layer is made from rapid thermal oxidation of W plugs. The device performs ...excellent electrical properties. The switching speed is extremely fast (${\sim}2$ ns) and the programming voltage (${<}1.4$ V) is low. For single-level cell (SLC) operation, the device shows a large resistance window, and $10^{8}$-cycle endurance. For multi-level cell (MLC) operation, it demonstrates 2-bit/cell storage with the endurance up to 10000 times. The rapid thermal oxidation (RTO) WO x resistance random access memory (RRAM) is very promising for both high-density and embedded memory applications.
Flash memory application has seen explosive growth in recent years and this trend is likely to continue because new and more demanding applications are constantly added partly due to the need for low ...power solid-state storage and partly due to rapidly declining prices. Conventional floating gate flash memories, no matter in NOR or NAND architecture, however, face steep challenges. For NOR flash, the junction breakdown and short channel effects have essentially squeezed out the device design space below 45
nm node. For NAND flash, the tight spacing, floating gate interference and the need for sufficient gate control (gate coupling ratio) have also ruled out the continuation of the conventional floating gate device below approximately 32
nm node. Charge trapping devices, exploiting high-K inter-poly dielectric (IPD) or by innovative tunneling barrier engineering, are proposed to continue scaling flash memories. Eventually, when too few electrons are stored and the logic level retention becomes smeared by statistical fluctuation over the life time of the device, 3-D layering of devices may provide the ultimate solution.
The erase characteristics and mechanism of metal- Al 2 O 3 -nitride-oxide-silicon (MANOS) devices are extensively studied. We use transient analysis to transform the erase curve (V FB - time) into a ...J-E curve (J = transient current, E = field in the tunnel oxide) in order to understand the underlying physics. The measured erase current of MANOS is three orders of magnitude higher than that can be theoretically provided by substrate hole current. In addition, the erase current is very sensitive to the Al 2 O 3 processing condition - also inconsistent with substrate hole injection model. Thus, we propose that MANOS erase occurs through an electron detrapping mechanism. We have further carried out a refill test and its results support the detrapping model. Our results suggest that the interfacial layer between Al 2 O 3 and nitride is a key process that dominates the erase mechanism of MANOS.
A single-sided PHINES SONOS memory with hot-hole injection in program operation and Fowler-Nordheim (FN) tunneling in erase operation has been demonstrated for high program speed and low power ...applications. High programming speed (/spl Delta/V T /program time) of 5 V/20 μs, low power consumption of P/E, high endurance of 10 K, good retention, and scaling capability can be demonstrated.
We have successfully developed a novel nitride-trapping non-volatile memory device using gate injection for program and erase operations. The device is a p-channel bandgap-engineered SONOS ...(BE-SONOS), but with ultra-thin ONO tunneling dielectric grown on top of the trapping nitride. Programming and erasing are by -FN electron injection and +FN hole injection from the poly gate, respectively. Since gate oxide is not used as the tunnel dielectric, it is spared of the program/erase current stressing, thus causes much less interface state generation after P/E cycling stressing. Very high endurance (10 M cycle P/E) is achieved owing to suppressed channel interface (S.S. and gm) degradation. Moreover, due to the gate injection instead of channel injection this novel device is insensitive to STI bird's beak geometry. Successful p-channel NAND array characteristics including the program inhibit and reading characteristics are demonstrated.
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