The ALICE collaboration is pursuing the development of a novel and considerably improved vertexing detector called ITS3, to replace the three innermost layers of the Inner Tracker System during the ...LHC Long Shutdown 3. The primary goals are to reduce the material budget to the unprecedented value of 0.05% X0 per layer, and to place the first layer at a radial distance of 18 mm from the interaction point. These features will boost the impact parameter resolution by a factor two over all momenta and drastically enhance the tracking efficiency at low transverse momentum.
The new detector will consist of true cylindrical layers. Each half-cylinder is based on curved wafer-scale monolithic pixel sensors. The bending radii are 18, 24 and 30 mm, and the length of the sensors in the beam direction is 27 cm. The sensors will be produced using a commercial 65 nm CMOS Imaging technology and a recent technique called stitching. This allows to manufacture chips reaching the dimensions of 27 cm × 9 cm on silicon wafers of 300 mm diameter. The sensors will be thinned down to 50 µm or below. The ITS3 concept foresees cooling by air flow, ultra-light carbon foam support elements and no flexible printed circuits in the active area. This demands a power density limit of 20 mW/cm2 for the sensor, and the need to distribute supply and transfer data over the entire sensors towards circuits located at the short edges of the chip.
This contribution summarises the status of the microelectronic developments and presents selected results from the characterisation of the first prototype chips. Furthermore, it describes the ongoing efforts on the design of a first wafer-scale stitched sensor prototype, the MOSS (Monolithic Stitched Sensor) chip.
For the upgrade of its Inner Tracking System, the ALICE experiment plans to install a new tracker fully constructed with monolithic active pixel sensors implemented in a standard 180 nm CMOS imaging ...sensor process, with a deep pwell allowing full CMOS within the pixel. Reverse substrate bias increases the tolerance to non-ionizing energy loss (NIEL) well beyond 10131MeVneq∕cm2, but does not allow full depletion of the sensitive layer and hence full charge collection by drift, mandatory for more extreme radiation tolerance. This paper describes a process modification to fully deplete the epitaxial layer even with a small charge collection electrode. It uses a low dose blanket deep high energy n-type implant in the pixel array and does not require significant circuit or layout changes so that the same design can be fabricated both in the standard and modified process. When exposed to a 55Fe source at a reverse substrate bias of −6 V, pixels implemented in the standard and the modified process in a low and high dose variant for the deep n-type implant respectively yield a signal of about 115 mV, 110 mV and 90 mV at the output of a follower circuit. Signal rise times heavily affected by the speed of this circuit are 27.8+∕−5 ns, 23.2+∕−4.2 ns, and 22.2+∕−3.7 ns rms, respectively. In a different setup, the single pixel signal from a 90Sr source only degrades by less than 20% for the modified process after a 10151MeVneq∕cm2 irradiation, while the signal rise time only degrades by about 16+∕−2 ns to 19+∕−2.8 ns rms. From sensors implemented in the standard process no useful signal could be extracted after the same exposure. These first results indicate the process modification maintains low sensor capacitance, improves timing performance and increases NIEL tolerance by at least an order of magnitude.
We derive expressions for the time resolution of silicon detectors, using the Landau theory and a PAI model for describing the charge deposit of high energy particles. First we use the centroid time ...of the induced signal and derive analytic expressions for the three components contributing to the time resolution, namely charge deposit fluctuations, noise and fluctuations of the signal shape due to weighting field variations. Then we derive expressions for the time resolution using leading edge discrimination of the signal for various electronics shaping times. Time resolution of silicon detectors with internal gain is discussed as well.
We derive expressions for the potential of a point charge as well as the weighting potential and weighting field of a rectangular pad for a plane condenser, which are well suited for numerical ...evaluation. We relate the expressions to solutions employing the method of image charges, which allows discussion of convergence properties and estimation of errors, providing also an illuminating example of a problem with an infinite number of image charges.
Abstract Early measurements on monolithic pixel sensor prototypes in the TPSCo 65 nm technology indicate a different response and radiation tolerance (up to 5×10 15 1 MeV n eq cm) for different ...sensor layout and process variants, illustrating the importance of layout and process in the path towards increased sensor radiation tolerance. Using these measurement results, TCAD simulations provide more insight to link the macroscopic behaviour of specific sensor variants to the details of its structure. With this insight we can propose a new variant combining the advantages of several measured variants as a path to even better radiation tolerance for the next iteration.
Abstract
The Digital Pixel Test Structure (DPTS) is a monolithic active pixel sensor prototype chip designed to explore the TPSCo 65 nm ISC process in the framework of the CERN-EP R&D on monolithic ...sensors and the ALICE ITS3 upgrade. It features a 32 × 32 binary pixel matrix at 15 μm pitch with event-driven readout, with GHz range time-encoded digital signals including Time-Over-Threshold. The chip proved fully functional and efficient in testbeam allowing early verification of the complete sensor to readout chain. This paper focuses on the design, in particular the digital readout and its perspectives with some supporting results.
This paper presents the design of a front-end circuit for monolithic active pixel sensors. The circuit operates with a sensor featuring a small, low-capacitance (< 2 fF) collection electrode and is ...integrated in the DPTS chip, a proof-of-principle prototype of 1.5 mm × 1.5 mm including a matrix of 32 × 32 pixels with a pitch of 15 μm. The chip is implemented in the 65 nm imaging technology from the Tower Partners Semiconductor Co. foundry and was developed in the framework of the EP-R&D program at CERN to explore this technology for particle detection. The front-end circuit has an area of 42 μm 2 and can operate with a power consumption as low as 12 nW. Measurements on the prototype relevant to the front-end will be shown to support its design.
Abstract
The MOnolithic Stitched Sensor (MOSS) is a development prototype chip towards the ITS3 vertexing detector for the ALICE experiment at the LHC. Designed using a 65 nm CMOS Imaging technology, ...it aims at profiting from the stitching technique to construct a single-die monolithic pixel detector of 1.4 cm × 26 cm. The MOSS prototype is one of the prototypes developed within the CERN-EP R&D framework to learn how to make stitched wafer-scale sensors with satisfactory yield. This contribution will describe some of the design challenges of a stitched pixel sensor and the techniques adopted during the development of this prototype.
Abstract
A series of monolithic active pixel sensor prototypes (APTS chips) were manufactured in the TPSCo 65 nm CMOS imaging process in the framework of the CERN-EP R&D on monolithic sensors and the ...ALICE ITS3 upgrade project. Each APTS chip contains a 4 × 4 pixel matrix with fast analog outputs buffered to individual pads. To explore the process and sensor characteristics, various pixel pitches (10 µm–25 µm), geometries and reverse biasing schemes were included. Prototypes are fully functional with detailed sensor characterization ongoing. The design will be presented with some experimental results also correlating to some transistor measurements.
TDCpix pixel detector ASIC with 100 ps time stamping Rinella, G. Aglieri; Bonacini, S.; Jarron, P. ...
Nuclear instruments & methods in physics research. Section A, Accelerators, spectrometers, detectors and associated equipment,
08/2023, Letnik:
1053
Journal Article
Recenzirano
Odprti dostop
The TDCpix pixel read-out ASIC contains 1800 pixels arranged in 40 columns and 45 rows with the dimension of 300μm x 300μm. Each pixel contains a preamplifier and shaper circuit with a dynamic range ...of 0.8 to 10 fC and a rise time of 5 ns, followed by a Leading-Edge discriminator with Time-over-Threshold correction. The discriminator outputs of each pixel are connected to time-to-digital converters (TDC) measuring the time when the input signal has exceeded the threshold and the pulse width with a binning of 97 ps. The electronics noise of pre-amplifier/shaper is 170 e− or 2.7 mV rms with a gain of 65 mV/fC. The jitter of the entire processing chain for an electrical input signal of 2.4 fC is lower than 60 ps rms. The ASIC has been designed to work in radiated environments of 6 * 104 Gray per year and 2 x 1014 1 MeV neutron equivalent cm−2.
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