Abstract A gap currently exists in our understanding of causes of elevated total circulating DNA (cirDNA) levels in cancer patients following tumor resection, and the influence of anesthesia or ...surgery on cirDNA release. Indeed, the post-surgery dynamics of cirDNA have been largely overlooked to date, despite their importance in determining the optimal timing for assessment of minimal residual disease (MRD). Since cirDNA levels were recently found to be associated with neutrophil extracellular traps (NETs) formation in various cancers, we investigated NETs and cirDNA post-surgery.We conducted two clinical studies to explore the dynamics of cirDNA quantity and of neutrophil extracellular traps (NETs) markers: (1) a peri-surgery study over a duration of up to 72 hours, which involved stage I-III colon (n=10), prostate (n=10), and breast (n=9) cancer patients; and (2) a post-surgery study that extended up to two years post-surgery, and which involved 74 stage III colon cancer patients. We assessed plasma levels of cirDNA using qPCR, and assessed two protein markers of NETs using ELISA, in both cancer patients and control group of healthy individuals (HI) (N=114). This second study is the first prospective, multicenter, blinded study of the dynamics of the total cirDNA post-surgery, for a period of up to two years.We observed that (i), NETs formation contributes to post-surgery conditions; (ii), peri- and post-surgery cirDNA levels were highly associated with NETs formation in colon cancer; (iii), each tumor type showed a specific pattern of the peri-surgery dynamics of cirDNA and NETs markers; peri-operative levels of these markers are significantly lower in breast cancer patients as compared to prostate and colorectal cancer patients; (iv), a significant proportion of patients showed pre- (58.1%) and post-surgery (80.4%) median marker values higher than in HI, even after 2 years following tumor resection, (v) these markers were either equal to or greater (23.2%) than their pre-surgery counterparts; and (vi), elevated values of these markers did not derive from chemotherapy toxicity.We provide evidence that, for cancer patients in the post-surgery period, cirDNA originates mainly from NETs. This finding calls into question the current method of assessing MRD according to the fraction of mutant cirDNA, given that the level of NETs formation appears to be patient dependant. The peri-surgery dynamics of NETs formation and cirDNA release vary according to the surgical procedure and cancer type. In a significant part of patients with colon cancer, NETs continue to persist for more than a year after surgery, irrespective of disease progression or chemotherapy use. Nevertheless, cirDNA and NETs marker levels vary in cases with post-surgery inflammatory/thrombotic adverse events. Our work highlights the existence of long-lasting “sequelae” effects of cancer, previously unreported. Citation Format: Andrei Kudriavtsev, Alexia Mirandola, Catalina I. Cofre Muñoz, Raquel Comas Navarro, Marco Macagno, Brice Pastor, Ekaterina Pisareva, Mireia Sanchis Marin, Javier Gonzalo Ruiz, Anna Sapino, Alice Bartolini, Massimo Di Maio, Cynthia Sanchez, Yann Gricourt, Xavier Capdevila, Gerald Lossaint, Evelyne Crapez, Marc Ychou, Ramon Salazar Soler, Elisabetta Fenocchio, Paula X. Fernandez Calotti, Philippe Cuvillon, Thibault Mazard, Cristina Santos Vivas, Elez M. Elez, Federica Di Nicolantonio, Alain R. Thierry. Post-surgery sequelae unrelated to disease progression and chemotherapy revealed in follow-up of stage III colon cancer patients abstract. In: Proceedings of the American Association for Cancer Research Annual Meeting 2024; Part 1 (Regular Abstracts); 2024 Apr 5-10; San Diego, CA. Philadelphia (PA): AACR; Cancer Res 2024;84(6_Suppl):Abstract nr 1026.
This paper presents the implementation by the students of a complex calculator in hardware. This project meets hardware design goals, and also highly motivates them to use competences learned in ...others subjects. The learning process, associated to System Design, is hard enough because the students have to deal with parallel execution, signal delay, synchronization … Then, to strengthen the knowledge of hardware design a methodology as project based learning (PBL) is proposed. Moreover, it is also used to reinforce cross subjects like math and software programming. This methodology creates a course dynamics that is closer to a professional environment where they will work with software and mathematics to resolve the hardware design problems. The students design from zero the functionality of the calculator. They are who make the decisions about the math operations that it is able to resolve it, and also the operands format or how to introduce a complex equation into the calculator. This will increase the student intrinsic motivation. In addition, since the choices may have consequences on the reliability of the calculator, students are encouraged to program in software the decisions about how implement the selected mathematical algorithm. Although math and hardware design are two tough subjects for students, the perception that they get at the end of the course is quite positive.
In this paper, we present an approach to the problem of low energy data scheduling for reconfigurable architectures targeting digital signal processing (DSP) and multimedia applications. The main ...goal is the reduction of the energy consumed by these applications through the integration of the proposed data management framework within a compilation tool specifically conceived for these architectures. Two levels of on-chip data storage are assumed to be available in the reconfigurable architecture. Then, the data manager tries to optimally exploit this storage hierarchy by saving data transfers among on-chip and external memories, so reducing the energy consumption. To do that, specific algorithms for finding the data shared among the different computation kernels of the application have been developed. Also, a data placement and replacement policy has been designed. We also show how an adequate data scheduling could decrease the number of operations required to implement the dynamic reconfiguration of the system.
The present study describes the oxygen uptake and total energy expenditure (including both aerobic and anaerobic contribution) response during three different circuit weight training (CWT) protocols ...of equivalent duration composed of free weight exercises, machine exercises, and a combination of free weight exercises intercalating aerobic exercise.
Controlled, randomized crossover designs.
Subjects completed in a randomized order three circuit weight training protocols of the same duration (3 sets of 8 exercises, 45min 15s) and intensity (70% of 15 repetitions maximum). The circuit protocols were composed of free weight exercises, machine exercises, or a combination of free weight exercises with aerobic exercise. Oxygen consumption and lactate concentration were measured throughout the circuit to estimate aerobic and anaerobic energy expenditure respectively.
Energy expenditure is higher in the combined exercise protocol (29.9±3.6 ml/kg/min), compared with Freeweight (24.2±2.8ml/kg/min) and Machine (20.4±2.9ml/kg/min). The combined exercise protocol produced the highest total energy expenditure but the lowest lactate concentration and perceived exertion. The anaerobic contribution to total energy expenditure was higher in the machine and free weight protocols compared with the combined exercise protocol (6.2%, 4.6% and 2.3% respectively).
In the proposed protocols, the combined exercise protocol results in the highest oxygen consumption. Total energy expenditure is related to the type of exercise included in the circuit. Anaerobic contributions to total energy expenditure during circuit weight training may be modest, but lack of their estimation may underestimate total energy expenditure.
ClinicalTrials.gov NCT01116856.
Celotno besedilo
Dostopno za:
DOBA, IZUM, KILJ, NUK, PILJ, PNG, SAZU, SIK, UILJ, UKNU, UL, UM, UPUK
The authors present a scheduling methodology for conditional execution of kernels onto single instruction stream/multiple data stream multicontext reconfigurable architectures. Data flow graphs are ...used to describe the target applications, in which some kernels are conditionally executed depending on runtime conditions. Immediately after testing a condition, the next kernel to be processed is known and its configurations and input data can be loaded, producing a computation stall while these transfers are performed. A compilation-time kernel scheduling is proposed to handle conditional branches (CB) by determining a kernel sequence that minimises these computation stalls reducing the application latency. Target applications are firstly partitioned taking into account the presence of CBs, and then kernels are ordered for execution and mapped onto the reconfigurable system. Experimental results obtained for interactive and synthetic applications demonstrate the effectiveness of the proposal.
This paper presents a new technique to improve the efficiency of data scheduling for multi-context reconfigurable architectures targeting multimedia and DSP applications. The main goal is to improve ...application energy consumption. Two levels of on-chip data storage are assumed in the reconfigurable architecture. The Data Scheduler attempts to optimally exploit this storage, by deciding in which on-chip memory the data have to be stored in order to reduce energy consumption. We also show that a suitable data scheduling could decrease the energy required to implement the dynamic reconfiguration of the system.
A new technique is presented in this paper to improve the efficiency of data scheduling for multi-context reconfigurable architectures targeting multimedia and DSP applications. The main goal is to ...improve the applications execution time minimizing external memory transfers. Some amount of on-chip data storage is assumed to be available in the reconfigurable architecture. Therefore the Complete Data Scheduler tries to optimally exploit this storage, saving data and result transfers between on-chip and external memories. In order to do this, specific algorithms for data placement and replacement have been designed. We also show that a suitable data scheduling could decrease the number of transfers required to implement the dynamic reconfiguration of the system.
MorphoSys is a reconfigurable SIMD architecture. In this paper, a BSP-based ray tracing is gracefully mapped onto MorphoSys. The mapping highly exploits ray-tracing parallelism. A straightforward ...mechanism is used to handle irregularity among parallel rays in BSP. To support this mechanism, a special data structure is established, in which no intermediate data has to be saved. Moreover, optimizations such as object reordering and merging are facilitated. Data starvation is avoided by overlapping data transfer with intensive computation so that applications with different complexity can be managed efficiently. Since MorphoSys is small in size and power efficient, we demonstrate that MorphoSys is an economic platform for 3D animation applications on portable devices.
This paper presents an architecture for running interactive ray tracing applications on portable devices such as cell phones, PDAs, and head mounted displays and discusses the main issues related to ...the mapping of this graphics algorithm using fixed-point arithmetic. The paper shows that a floating-point arithmetic unit, with its associated power and area consumption, can be avoided by using appropriate fixed-point arithmetic and block floating-point operations. It is also shown that a computation intensive graphics method like ray tracing can be used to generate simple images at interactive rates on portable devices. This can be achieved by employing a reconfigurable SIMD architecture on a chip, which trades parallelism for frequency of operation, thus providing significant benefits in power saving, which is essential in portable devices.
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