Imaging temperature fields at the nanoscale is a central challenge in various areas of science and technology. Nanoscopic hotspots, such as those observed in integrated circuits or plasmonic ...nanostructures, can be used to modify the local properties of matter, govern physical processes, activate chemical reactions and trigger biological mechanisms in living organisms. The development of high-resolution thermometry techniques is essential for understanding local thermal non-equilibrium processes during the operation of numerous nanoscale devices. Here we present a technique to map temperature fields using a scanning thermal microscope. Our method permits the elimination of tip-sample contact-related artefacts, a major hurdle that so far has limited the use of scanning probe microscopy for nanoscale thermometry. We map local Peltier effects at the metal-semiconductor contacts to an indium arsenide nanowire and self-heating of a metal interconnect with 7 mK and sub-10 nm spatial temperature resolution.
Additional functionalities on semiconductor microchips are progressively important in order to keep up with the ever-increasing demand for more powerful computational systems. Monolithic III–V ...integration on Si promises to merge mature Si CMOS processing technology with III–V semiconductors possessing superior material properties, e.g., in terms of carrier mobility or band structure (direct band gap). In particular, Si photonics would strongly benefit from an integration scheme for active III–V optoelectronic devices in order to enable low-cost and power-efficient electronic–photonic integrated circuits. We report on room-temperature lasing from AlGaAs/GaAs microdisk cavities monolithically integrated on Si(001) using a selective epitaxial growth technique called template-assisted selective epitaxy. The grown gain material possesses high optical quality without indication of threading dislocations, antiphase boundaries, or twin defects. The devices exhibit single-mode lasing at T < 250 K and lasing thresholds between 2 and 18 pJ/pulse depending on the cavity size (1–3 μm in diameter).
The seamless integration of III-V nanostructures on silicon is a long-standing goal and an important step towards integrated optical links. In the present work, we demonstrate scaled and waveguide ...coupled III-V photodiodes monolithically integrated on Si, implemented as InP/In
Ga
As/InP p-i-n heterostructures. The waveguide coupled devices show a dark current down to 0.048 A/cm
at -1 V and a responsivity up to 0.2 A/W at -2 V. Using grating couplers centered around 1320 nm, we demonstrate high-speed detection with a cutoff frequency f
exceeding 70 GHz and data reception at 50 GBd with OOK and 4PAM. When operated in forward bias as a light emitting diode, the devices emit light centered at 1550 nm. Furthermore, we also investigate the self-heating of the devices using scanning thermal microscopy and find a temperature increase of only ~15 K during the device operation as emitter, in accordance with thermal simulation results.
We report complementary metal–oxide–semiconductor (CMOS)-compatible integration of compound semiconductors on Si substrates. InAs and GaAs nanowires are selectively grown in vertical SiO2 nanotube ...templates fabricated on Si substrates of varying crystallographic orientations, including nanocrystalline Si. The nanowires investigated are epitaxially grown, single-crystalline, free from threading dislocations, and with an orientation and dimension directly given by the shape of the template. GaAs nanowires exhibit stable photoluminescence at room temperature, with a higher measured intensity when still surrounded by the template. Si–InAs heterojunction nanowire tunnel diodes were fabricated on Si(100) and are electrically characterized. The results indicate a high uniformity and scalability in the fabrication process.
The operation of electronic devices relies on the density of free charge carriers available in the semiconductor; in most semiconductor devices this density is controlled by the addition of doping ...atoms. As dimensions are scaled down to achieve economic and performance benefits, the presence of interfaces and materials adjacent to the semiconductor will become more important and will eventually completely determine the electronic properties of the device. To sustain further improvements in performance, novel field-effect transistor architectures, such as FinFETs and nanowire field-effect transistors, have been proposed as replacements for the planar devices used today, and also for applications in biosensing and power generation. The successful operation of such devices will depend on our ability to precisely control the location and number of active impurity atoms in the host semiconductor during the fabrication process. Here, we demonstrate that the free carrier density in semiconductor nanowires is dependent on the size of the nanowires. By measuring the electrical conduction of doped silicon nanowires as a function of nanowire radius, temperature and dielectric surrounding, we show that the donor ionization energy increases with decreasing nanowire radius, and that it profoundly modifies the attainable free carrier density at values of the radius much larger than those at which quantum and dopant surface segregation effects set in. At a nanowire radius of 15 nm the carrier density is already 50% lower than in bulk silicon due to the dielectric mismatch between the conducting channel and its surroundings.
Abstract The chiral anomaly - a hallmark of chiral spin-1/2 Weyl fermions - is an imbalance between left- and right-moving particles that underpins phenomena such as particle decay and negative ...longitudinal magnetoresistance in Weyl semimetals. The discovery that chiral crystals can host higher-spin generalizations of Weyl quasiparticles without high-energy counterparts, known as multifold fermions, raises the fundamental question of whether the chiral anomaly is a more general phenomenon. Answering this question requires materials with chiral quasiparticles within a sizable energy window around the Fermi level that are unaffected by extrinsic effects such as current jetting. Here, we report the chiral anomaly of multifold fermions in CoSi, which features multifold bands within ~0.85 eV of the Fermi level. By excluding current jetting through the squeezing test, we measure an intrinsic, longitudinal negative magnetoresistance. We develop a semiclassical theory to show that the negative magnetoresistance originates in the chiral anomaly, despite a sizable and detrimental orbital magnetic moment contribution. A concomitant non-linear Hall effect supports the multifold-fermion origin of the magnetotransport. Our work confirms the chiral anomaly of higher-spin generalizations of Weyl fermions, currently inaccessible outside solid-state platforms.
Photonic crystal (PhC) cavities are promising candidates for Si photonics integrated circuits due to their ultrahigh quality (Q)-factors and small mode volumes. Here, we demonstrate a novel concept ...of a one-dimensional hybrid III–V/Si PhC cavity which exploits a combination of standard silicon-on-insulator technology and active III–V materials. Using template-assisted selective epitaxy, the central part of a Si PhC lattice is locally replaced with III–V gain material. The III–V material is placed to overlap with the maximum of the cavity mode field profile, while keeping the major part of the PhC in Si. The selective epitaxy process enables growth parallel to the substrate, and hence in-plane integration with Si, and in-situ in-plane homo- and heterojunctions. The fabricated hybrid III–V/Si PhCs show emission over the entire telecommunication band from 1.2 to 1.6 μm at room temperature validating the device concept and its potential towards fully integrated light sources on silicon.
III-V semiconductors are being considered as promising candidates to replace silicon channel for low-power logic and RF applications in advanced technology nodes. InGaAs is particularly suitable as ...the channel material in n-type metal-oxide-semiconductor field-effect transistors (MOSFETs), due to its high electron mobility. In the present work, we report on InGaAs FinFETs monolithically integrated on silicon substrates. The InGaAs channels are created by metal⁻organic chemical vapor deposition (MOCVD) epitaxial growth within oxide cavities, a technique referred to as template-assisted selective epitaxy (TASE), which allows for the local integration of different III-V semiconductors on silicon. FinFETs with a gate length down to 20nm are fabricated based on a CMOS-compatible replacement-metal-gate process flow. This includes self-aligned source-drain n⁺ InGaAs regrown contacts as well as 4 nm source-drain spacers for gate-contacts isolation. The InGaAs material was examined by scanning transmission electron microscopy (STEM) and the epitaxial structures showed good crystal quality. Furthermore, we demonstrate a controlled InGaAs digital etching process to create doped extensions underneath the source-drain spacer regions. We report a device with gate length of 90 nm and fin width of 40 nm showing on-current of 100 µA/µm and subthreshold slope of about 85 mV/dec.
Semiconductor transistors operate by modulating the charge carrier concentration of a channel material through an electric field coupled by a capacitor. This mechanism is constrained by the ...fundamental transport physics and material properties of such devices-attenuation of the electric field, and limited mobility and charge carrier density in semiconductor channels. In this work, we demonstrate a new type of transistor that operates through a different mechanism. The channel material is a Weyl semimetal, NbP, whose resistivity is modulated via a magnetic field generated by an integrated superconductor. Due to the exceptionally large electron mobility of this material, which reaches over 1,000,000 cm
/Vs, and the strong magnetoresistive coupling, the transistor can generate significant transconductance amplification at nanowatt levels of power. This type of device can enable new low-power amplifiers, suitable for qubit readout operation in quantum computers.
InGaAs is a potential candidate for Si replacement in upcoming advanced technological nodes because of its excellent electron transport properties and relatively low interface defect density in ...dielectric gate stacks. Therefore, integrating InGaAs devices with the established Si platforms is highly important. Using template-assisted selective epitaxy (TASE), InGaAs nanowires can be monolithically integrated with high crystal quality, although the mechanisms of group III incorporation in this ternary material have not been thoroughly investigated. Here we present a detailed study of the compositional variations of InGaAs nanostructures epitaxially grown on Si(111) and Silicon-on-insulator substrates by TASE. We present a combination of XRD data and detailed EELS maps and find that the final Ga/In chemical composition depends strongly on both growth parameters and the growth facet type, leading to complex compositional sub-structures throughout the crystals. We can further conclude that the composition is governed by the facet-dependent chemical reaction rates at low temperature and low V/III ratio, while at higher temperature and V/III ratio, the incorporation is transport limited. In this case we see indications that the transport is a competition between Knudsen flow and surface diffusion.
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