Bipolar resistive switching (BRS) cells based on the valence change mechanism show great potential to enable the design of future non-volatile memory, logic and neuromorphic circuits and ...architectures. To study these circuits and architectures, accurate compact models are needed, which showcase the most important physical characteristics and lead to their specific experimental behavior. If BRS cells are to be used for computation-in-memory or for neuromorphic computing, their dynamical behavior has to be modeled with special consideration of switching times in SET and RESET. For any realistic assessment, variability has to be considered additionally. This study shows that by extending an existing compact model, which by itself is able to reproduce many different experiments on device behavior critical for the anticipated device purposes, variability found in experimental measurements can be reproduced for important device characteristics such as I-V characteristics, endurance behavior and most significantly the SET and RESET kinetics. Furthermore, this enables the study of spatial and temporal variability and its impact on the circuit and system level.
Redox-based resistive switching random access memory (ReRAM) offers excellent properties to implement future non-volatile memory arrays. Recently, the capability of two-state ReRAMs to implement ...Boolean logic functionality gained wide interest. Here, we report on seven-states Tantalum Oxide Devices, which enable the realization of an intrinsic modular arithmetic using a ternary number system. Modular arithmetic, a fundamental system for operating on numbers within the limit of a modulus, is known to mathematicians since the days of Euclid and finds applications in diverse areas ranging from e-commerce to musical notations. We demonstrate that multistate devices not only reduce the storage area consumption drastically, but also enable novel in-memory operations, such as computing using high-radix number systems, which could not be implemented using two-state devices. The use of high radix number system reduces the computational complexity by reducing the number of needed digits. Thus the number of calculation operations in an addition and the number of logic devices can be reduced.
The inevitable variability within electronic devices causes strict constraints on operation, reliability and scalability of the circuit design. However, when a compromise arises among the different ...performance metrics, area, time and energy, variability then loosens the tight requirements and allows for further savings in an alternative design scope. To that end, unconventional computing approaches are revived in the form of approximate computing, particularly tuned for resource-constrained mobile computing. In this paper, a proof-of-concept of the approximate computing paradigm using memristors is demonstrated. Stochastic memristors are used as the main building block of probabilistic logic gates. As will be shown in this paper, the stochasticity of memristors' switching characteristics is tightly bound to the supply voltage and hence to power consumption. By scaling of the supply voltage to appropriate levels stochasticity gets increased. In order to guide the design process of approximate circuits based on memristors a realistic device model needs to be elaborated with explicit emphasis of the probabilistic switching behavior. Theoretical formulation, probabilistic analysis, and simulation of the underlying logic circuits and operations are introduced. Moreover, the expected output behavior is verified with the experimental measurements of valence change memory cells. Hence, it is shown how the precision of the output is varied for the sake of the attainable gains at different levels of available design metrics. This approach represents the first proposition along with physical verification and mapping to real devices that combines stochastic memristors into unconventional computing approaches.
Rapid growth of future information technology depends on energy‐efficient computation and ultra‐high density data storage. Non‐volatile redox‐based resistive switching memory (ReRAM) devices offer ...logic‐in‐memory capabilities and can redefine the von Neumann computer architecture. Especially complementary resistive switches (CRSs) enable the integration of highly dense passive nano‐crossbar arrays in 4F2 structure (F is the minimum feature size) without the need of selector devices. To reduce fabrication complexity further, single ReRAM device in complementary switching (CS) mode is a viable option. Here, the implementation of in‐memory‐adders using Pt|HfO2|Hf|Pt‐based CS devices, which are integrated into 1 × n passive crossbar arrays, is reported. First, the feasibility of all CRS‐logic functions with these CS devices is shown, which offer high‐endurance (109 cycles) under pulse conditions. Afterward, two multi‐bit crossbar adders, the Toggle‐Cell Adder and the Pre‐Calculation Adder, are experimentally demonstrated under pulse conditions realizing addition and subtraction operations. These results prove the functional efficiency of the crossbar adder approach, paving the path for highly advanced ReRAM‐based computing‐in‐memory architectures.
Complementary switching (CS) devices offer beyond‐memory capabilities, i.e., implementation of addition and subtraction operations locally within passive crossbar arrays, which are based on the complementary resistive switch (CRS)‐logic‐in‐memory concept. The CS device is realized by the Pt|HfO2|Hf|Pt stack and provides stable switching with high endurance. The functionality of two different types of multibit crossbar adders under pulse conditions is demonstrated experimentally.
Highly accurate and predictive models of resistive switching devices are needed to enable future memory and logic design. Widely used is the memristive modeling approach considering resistive ...switches as dynamical systems. Here we introduce three evaluation criteria for memristor models, checking for plausibility of the I-V characteristics, the presence of a sufficiently nonlinearity of the switching kinetics, and the feasibility of predicting the behavior of two antiserially connected devices correctly. We analyzed two classes of models: the first class comprises common linear memristor models and the second class widely used nonlinear memristive models. The linear memristor models are based on Strukov's initial memristor model extended by different window functions, while the nonlinear models include Pickett's physics-based memristor model and models derived thereof. This study reveals lacking predictivity of the first class of models, independent of the applied window function. Only the physics-based model is able to fulfill most of the basic evaluation criteria.
Redox-based resistive switching devices (ReRAM) are an emerging class of nonvolatile storage elements suited for nanoscale memory applications. In terms of logic operations, ReRAM devices were ...suggested to be used as programmable interconnects, large-scale look-up tables or for sequential logic operations. However, without additional selector devices these approaches are not suited for use in large scale nanocrossbar memory arrays, which is the preferred architecture for ReRAM devices due to the minimum area consumption. To overcome this issue for the sequential logic approach, we recently introduced a novel concept, which is suited for passive crossbar arrays using complementary resistive switches (CRSs). CRS cells offer two high resistive storage states, and thus, parasitic "sneak" currents are efficiently avoided. However, until now the CRS-based logic-in-memory approach was only shown to be able to perform basic Boolean logic operations using a single CRS cell. In this paper, we introduce two multi-bit adder schemes using the CRS-based logic-in-memory approach. We proof the concepts by means of SPICE simulations using a dynamical memristive device model of a ReRAM cell. Finally, we show the advantages of our novel adder concept in terms of step count and number of devices in comparison to a recently published adder approach, which applies the conventional ReRAM-based sequential logic concept introduced by Borghetti et al.
Emerging resistively switching devices are thought to enable ultradense passive nanocrossbar arrays for use as random access memories (ReRAM) by the end of the decade, both for embedded and mass ...storage applications. Moreover, ReRAMs offer inherent logic‐in‐memory (LIM) capabilities due to the nonvolatility of the devices and therefore great potential to reduce the communication between memory and calculation unit by alleviating the so‐called von Neumann bottleneck. A single bipolar resistive switching device is capable of performing 14 of 16 two input logic functions in the logic concept presented by Linn et al. (“CRS‐logic”). In this paper, five types of selectorless devices are considered to validate this CRS‐logic concept is experimentally by means of the IMP and AND logic operations. As reference device a TaO
x
‐based ReRAM cell is considered, which is compared to three more advanced device configurations consisting either of a threshold supported resistive switch (TS‐ReRAM), a complementary switching device (CS), or a complementary resistive switch (CRS). It is shown that all of these devices offer the desired LIM behavior. Moreover, the feasibility of XOR and XNOR operations using a modified logic concept is applied for both CS and CRS devices and the pros and cons are discussed.
Resistive switching devices enable sequential logic‐in‐memory operations. The feasibility of 14 of 16 two input Boolean logic functions is proven experimentally for: redox‐based resistive switching cells (ReRAMs), ReRAMs offering inherent threshold switching, ReRAMs offering complementary switching (CS), and complementary resistive switching (CRS) cells. Moreover, it is shown that CS and CRS cells also enable the two remaining functions, XOR and XNOR.
The Programmable Logic-in-Memory (PLiM) computer Gaillardon, Pierre-Emmanuel; Amaru, Luca; Siemon, Anne ...
2016 Design, Automation & Test in Europe Conference & Exhibition (DATE),
03/2016
Conference Proceeding, Journal Article
Realization of logic and storage operations in memristive circuits have opened up a promising research direction of in-memory computing. Elementary digital circuits, e.g., Boolean arithmetic ...circuits, can be economically realized within memristive circuits with a limited performance overhead as compared to the standard computation paradigms. This paper takes a major step along this direction by proposing a fully-programmable in-memory computing system. In particular, we address, for the first time, the question of controlling the in-memory computation, by proposing a lightweight unit managing the operations performed on a memristive array. Assembly-level programming abstraction is achieved by a natively-implemented majority and complement operator. This platform enables diverse sets of applications to be ported with little effort. As a case study, we present a standardized symmetric-key cipher for lightweight security applications. The detailed system design flow and simulation results with accurate device models are reported validating the approach.
Redox-based resistive switches are an emerging class of non-volatile memory and logic devices. Especially, ultimately scaled transistor-less passive crossbar arrays using a selector/resistive-switch ...(1S1R) configuration are one of the most promising architectures. Due to the scalability and the inherent logic and memory capabilities of these devices, they are good candidates for logic-in-memory approaches. But due to the memory architecture, true parallelism can only be achieved by either working on several arrays at the same time or at multiple lines in an array at the same time. In this work, a Sklansky tree adder is presented, which exploits the parallelism of a single crossbar array. The functionality is proven by means of memristive simulations using a physics-based TaO
x
model. The circuit and device requirements for this approach are discussed.
The multidisciplinary field of memristors calls for the necessity for theoretically‐inclined researchers and experimenters to join forces, merging complementary expertise and technical know‐how, to ...develop and implement rigorous and systematic techniques to design variability‐aware memristor‐based circuits and systems. The availability of a predictive physics‐based model for a memristor is a necessary requirement before commencing these investigations. An interesting dynamic phenomenon, occurring ubiquitously in non‐volatile memristors, is fading memory. The latter may be defined as the appearance of a unique steady‐state behavior, irrespective of the choice of the initial condition from an admissible range of values, for each stimulus from a certain family, for example, the DC or the purely‐AC periodic input class. This paper first provides experimental evidence for the emergence of fading memory effects in the response of a TaOx redox‐based random access memory cell to inputs from both of these classes. Leveraging the predictive capability of a physics‐based device model, called JART VCM v1, a thorough system‐theoretic analysis, revolving around the Dynamic Route Map graphic tool, is presented. This analysis allows to gain a better understanding of the mechanisms, underlying the emergence of history erase effects, and to identify the main factors, that modulate this nonlinear phenomenon, toward future potential applications.
This paper employs theoretic methods to gain a deep insight into the resistance switching phenomena emerging in a representative redox‐based random access memory cell. The application of a powerful analysis tool to an accurate physics‐based device model enables to understand the complex mechanisms, which induce memory loss in the non‐volatile memristor under both SET and RESET stimuli, opening up new interesting application scenarios.
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