Metastasis is the main cause of tumor-related death, and the dispersal of tumor cells through the circulatory system is a critical step in the metastatic process. Early detection and analysis of ...circulating tumor cells (CTCs) is therefore important for early diagnosis, prognosis, and effective treatment of cancer, enabling favorable clinical outcomes in cancer patients. Accurate and reliable methods for isolating and detecting CTCs are necessary to obtain this clinical information. Over the past two decades, microfluidic technologies have demonstrated great potential for isolating and detecting CTCs from blood. The present paper reviews current advanced microfluidic technologies for isolating CTCs based on various biological and physical principles, and discusses their fundamental advantages and drawbacks for subsequent cellular and molecular assays. Owing to significant genetic heterogeneity among CTCs, microfluidic technologies for isolating individual CTCs have recently been developed. We discuss these single-cell isolation methods, as well as approaches to overcoming the limitations of current microfluidic CTC isolation technologies. Finally, we provide an overview of future innovative microfluidic platforms.
Ionic electroactive polymer (IEAP) actuators that are driven by electrical stimuli have been widely investigated for use in practical applications. However, conventional electrodes in IEAP actuators ...have a serious drawback of poor durability under long-term actuation in open air, mainly because of leakage of the inner electrolyte and hydrated cations through surface cracks on the metallic electrodes. To overcome this problem, a top priority is developing new high-performance ionic polymer actuators with graphene electrodes that have superior mechanical, electrical conductivity, and electromechanical properties. However, the task is made difficultby issues such as the low electrical conductivity of graphene (G). The percolation network of silver nanowires (Ag-NWs) is believed to enhance the conductivity of graphene, while poly(3,4-ethylenedioxythiophene):polystyrene sulfonate (PEDOT:PSS), which exhibits excellent stability under ambient conditions, is expected to improve the actuation performance of IEAP actuators. In this study, we developed a very fast, stable, and durable IEAP actuator by employing electrodes made of a nanocomposite comprising PEDOT:PSS and graphene⁻Ag-NWs (P/(G⁻Ag)). The cost-effective P/(G⁻Ag) electrodes with high electrical conductivity displayed a smooth surface resulting from the PEDOT:PSS coating, which prevented oxidation of the surface upon exposure to air, and showedstrong bonding between the ionic polymer and the electrode surface. More interestingly, the proposed IEAP actuator based on the P/G⁻Ag electrode can be used in active biomedical devices, biomimetic robots, wearable electronics, and flexible soft electronics.
The brain’s learning and adaptation processes heavily rely on the concept of associative memory. One of the most basic associative learning processes is classical conditioning. This work presents a ...memristive neural network-based associative memory system. The system can emulate Pavlovian conditioning principles including acquisition, extension, generalization, differentiation, and spontaneous recovery that have not been considered in most of the previous counterparts. The proposed circuit can emulate these principles thanks to the resistance-changing characteristics of the memristor. Generalization has been achieved by providing both unconditional and neutral stimuli to the network to reduce the memristance of the memristor. Differentiation has been attained by employing unconditional and conditional stimuli in a training scheme to obtain a certain memristance that causes the network to respond differently to both stimuli. A revival of an exterminated stimuli is also done by increasing the synaptic weight of the system. Compared to previous designs, the proposed memristive circuit can implement all the functions of conditional reflex. Our rigorous simulations demonstrated that the proposed memristive system can condition neutral stimuli, show generalization between similar stimuli, distinguish dissimilarities between the generalized stimuli, and recover faded stimuli.
This work reports in first time a 100-Gb/s, ultra-low noise, variable gain multi-stagger tuned transimpedance amplifier (VGMST-TIA) over the D-band performance. The whole work is binding into two ...phases. The first phase involves the modeling and characterization of graphene field-effect transistor (GFET) with an optimized transition frequency of operation. While in the second phase, a TIA design employs a T-shaped symmetrical L-R network at the input, which mitigates the effect of photo diode capacitance and achieves a D-band of operation. The proposed work uses a VGMST to establish TIA, which realizes optimum noise performance. The high gain 3-stage VGMST-TIA effectively minimizes the white noise and illustrates a sharp out-of-band roll-off to achieve considerable noise reduction at high frequencies. The active feedback mechanism controls the transimpedance gain by tuning the control voltage which results better group delay. Besides, an L-C circuit is employed at the output to enhance bandwidth. The full TIA is implemented and fabricated using a commercial nano-manufacturing 9-nm graphene film FET on a silicon wafer using 0.065-μm process. The TIA achieves a flat transimpedance gain of 61.2 dBΩ with ± 9 ps group delay variation over the entire bandwidth. The proposed TIA measured an impedance bandwidth of 0.2 THz with ultra-low input-referred noise current density of 2.03 pA/√Hz. The TIA supports a 100-Gb/s data transmission due to large bandwidth; therefore, a bit-error-rate (BER) less than 10
−12
is achieved. The chip occupies an area of 0.92 * 1.34 mm
2
while consuming power of 21 mW under supply of 1.8 V.
This paper presents a high-efficiency Class
FF
-
1
DPA using the quad-mode coupled technique for new configurable front-end 5G transmitters. The proposed DPA consists of carrier PA, main PA, ...input–output matching network and hybrid power network (HPN). The HPN includes a quad-mode coupled technique which is four-section U-shaped transmission line. The HPN is used for even–odd mode impedance analysis to ensures the high-selectivity of output power and achieve a wideband response in the presence of harmonic control conditions. The optimum harmonic impedance is analyzed for the desired band to achieve high output power and efficiency. The DPA circuit is fabricated by using 0.25 µm GaN HEMT on silicon nitride monolithic microwave integrated circuit die process. At maximum output power level of 44.3 dBm, the delivered power-added efficiency (PAE) of 64.3–67.3% and drain efficiency (DE) of 71.7–73.7% at even–odd mode operation are achieved with a gain of 13.0–14.3 dB. For the output power level of 39.045 dBm corresponding to 9 dB output back-off (OBO), the drain efficiency lies between 55–62% with 73% fractional bandwidth. All the demonstrated transmission parameters are working in the band of 8–12 GHz. The size of the chip is 2.8 × 1.9 mm
2
and it occupies less die area as compared to the existing DPAs.
In designing neuromorphic circuits and systems, developing compact and energy-efficient neuron and synapse circuits is essential for high-performance on-chip neural architectures. Toward that end, ...this work utilizes the advanced low-power and compact 7nm FinFET technology to design leaky integrate-and-fire (LIF) neuron and spike-timing-dependent plasticity (STDP) circuits. In the proposed STDP circuit, only six FinFETs and three small capacitors (two 10fF and 20fF) have been utilized to realize STDP learning. Moreover, 12 transistors and two capacitors (20fF) have been employed for designing the LIF neuron circuit. The evaluation results demonstrate that besides 60% area saving, the proposed STDP circuit achieves 68% improvement in total average power consumption and 43% lower energy dissipation compared to previous works. The proposed LIF neuron circuit demonstrates 34% area saving, 46% power, and 40% energy saving compared to its counterparts. The neuron can also tune the firing frequency within 5MHz-330MHz using an external control voltage. These results emphasize the potential of the proposed neuron and STDP learning circuits for compact and energy-efficient neuromorphic computing systems.
This article presents a K/Ka (18-40) GHz dual-band switch-free reconfigurable 65nm CMOS Low-Noise Amplifier (LNA) realized by inter-stage and output-stage Suspended-Substrate Coupled-Lines (SSCL) for ...the first time to the author's best knowledge. The amplified input signal from the broadband drive stage is divided into two parallel single band stages by the proposed inter-stage SSCL. Two split-band signals are amplified by the corresponding High-band (Ka) and Low-band (K) stages. The proposed output-stage SSCL combines the amplified two single-bands at the output. The proposed SSCL also provides the required network matching to the LNA. The single band of operation can be achieved by simply turning off the unused transistor band's drain voltage. The proposed LNA achieves a maximum noise figure (NF) taken in dual-mode of 1 dB and 1.2 dB and a gain of 27 dB with 0.2 dB and 2 dB variation in the K-band and Ka-band, respectively. Statistical analysis and design of experiment (DoE) are applied to predict the percentage error tolerance and validate the contribution of the parameters towards gain, return loss, and noise figure. This LNA exhibits an input and output 1-dB compression point (IP 1dB & OP 1dB ), third-order input & output intercept point (IIP 3 & OIP 3 ) of −17/−16 dBm, +7.1/6.4 dBm, 0 dBm and +25/+23 dBm over 18-24/25-40 GHz respectively. The fabricated LNA draws 21.4 mA from 1.2 V with a size of 0.61 <inline-formula> <tex-math notation="LaTeX">\times </tex-math></inline-formula> 0.92 mm 2 .
This study presents integration of complementary CMOS active feedback low noise amplifier with coplanar waveguide fed patch antenna for Wi‐Fi networks. The LNA design‐I, involves a cascode amplifier ...followed by active feedback common source amplifier offering wideband impedance matching with lowered parasitic losses. The inductor‐less feedback mechanism is used to nullify noise effect with extended bandwidth in the range of 2.2 to 5.8 GHz and a peak forward gain of 22.5 dB. It is implemented on agilent's advance design system using 45 nm CMOS process. The noise figure (NF) is approximately 2 dB while the stability factors µ and µ prime are well above 1 dB with IIP3 of about 15 dBm. The chip area is 0.57 x 0.57 mm2 under dc power supply of 1V while power consumption of 0.8 mW. A CPW fed antenna design‐II, achieves a wide band response similar to the bandwidth of LNA. The size of the fabricated antenna is calculated as 40 x 40 mm2. The peak gain is approximately 4.1 dBi at 3.9 GHz. The codesign‐III, proposes a receiver achieving a much wider band of 1.6 to 6 GHz with a gain of 16.5 dB and NF of 2.59 dB at 2.06 GHz. The codesign improves the system integration by reducing overall chip area and offers saving in the effective cost.
Despite the advantages of ternary logic, it has suffered from excessive transistor count and limited noise margin. This work proposes an ultra-efficient nonvolatile ternary flip-flop (FF) based on ...negative capacitance carbon nanotube field-effect transistors (NC-CNTFETs). By harnessing the negative differential resistance effect in NC-CNTFETs, the proposed design is similar to a conventional volatile binary FF regarding the number of transistors and control signals. During a scheduled power gating or a sudden power outage, the proposed ternary FF benefits from an auto-backup/auto-restore capability without employing any additional transistors, nonvolatile devices, or control signals. This leads to zero device overhead, which is a breakthrough in designing nonvolatile memory circuits. On the other hand, the back-to-back slave latch's hysteretic behavior provides an extraordinary static noise margin that transcends the noise margin of both conventional ternary and binary latches. The simulation results indicate that eliminating additional backup and restore circuitries provides 43% improvements in transistor count, 59% improvements in power saving and 98% improvements in energy-saving than state-of-the-art binary and ternary FFs. Moreover, the proposed design presents a 1.5 times higher static noise margin than the conventional binary and ternary FFs. Our proposed approach opens new doors in realizing ultra-efficient nonvolatile ternary circuits and systems in neuromorphic applications using ferroelectric-based transistors.
An ultra-low noise, Tera-ohm input impedance two-stage front-end neural amplifier (FENA) in the 28 nm CMOS process is presented in this work. As per the author’s best knowledge, the proposed FENA is ...implemented on a 28 nm CMOS process for the first time. The proposed FENA consists of an operational transconductance amplifier integrated low-pass filter (LPF) technique. This technique effectively removes the noise current density by using the LPF transfer function and FENA circuit to achieve the best performances, such as ultra-low input-referred noise, ultra-high input impedance, and high gain. The proposed mathematical technique is employed to optimize the dimensions of the neural amplifier in the 28 nm lower node, which results in a noise-free biasing current and ultra-low input referred noise of 18 at 10 KHz. The ultra-low input referred noise of FENA is achieved by reducing the gate-distributed resistance method. The FENA achieves an ultra-high input impedance of 0.2 Tera-ohm, while a splendid measured gain of 60 dB has succeeded. FENA occupies a chip area of 0.0023 mm2, which consumes a lower power consumption of 1 µW under supply voltage of 1.2 V. The FENA is found to be less prone to PVT variations as 1 mHz of high-pass corner frequency towards robust design. The best performance parameters of FENA could be beneficial for deep exploration neural recording in wireless neural monitoring systems. KCI Citation Count: 0
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