Degradation mechanisms associated to lateral isolation oxides are discussed to account for total ionizing dose effects on the noise performance of 90 nm and 130 nm CMOS devices and for their ...dependence on geometry and operating conditions. In NMOSFETs with a conventional open layout, after irradiation the parasitic transistor at the device edges turns on and contributes to the total device noise. The paper provides a model to help understanding the impact of this radiation-induced noise contribution on white and 1/f noise terms. The different behavior of NMOSFETs in the two examined technology nodes is analyzed in this framework, and design criteria to reduce noise degradation in irradiated devices are discussed.
In the last few years CMOS commercial technologies of the quarter micron node have been extensively used in the design of the readout electronics for highly granular detection systems in the particle ...physics environment. IC designers are now moving to 130 nm CMOS technologies, or even to the next technology generation, to implement readout integrated circuits for future HEP applications. In order to evaluate how scaling down of the device features affects their performances, continuous technology monitoring is mandatory. In this work the results of signal and noise measurements carried out on two CMOS commercial processes are presented. Data obtained from the measurements provide a powerful tool to establish design criteria in nanoscale CMOS processes for detector front-ends and can be used to evaluate the resolution limits achievable for low-noise charge sensitive amplifiers in the 100-nm minimum feature size range.
This paper presents a study of the noise behavior of submicron CMOS transistors, in view of applications to high-density mixed-signal front-end systems for high-granularity detectors. The goal of ...this work is extending the knowledge in this field, presently focused on 0.25 /spl mu/m processes, to the following generation of CMOS technologies (with 0.18 /spl mu/m minimum gate length). The white component of the noise voltage spectrum, which is most important for fast signal processing, and the 1/f noise contribution are experimentally characterized with noise measurements in a wide frequency range. The results of this analysis are used to establish low-noise design criteria concerning the choice of the polarity and of the channel dimensions (length and width) of the preamplifier input device in low-power operating conditions. A comparison with similar noise measurements on CMOS devices belonging to a 0.35 /spl mu/m process allows estimating the impact of gate-length scaling on both white and 1/f noise components. The noise radiation tolerance is also a key parameter for many front-end systems. It was evaluated by exposing the devices to high doses of ionizing radiation.
Submicrometer CMOS technologies provide well-established solutions to the implementation of low-noise front-end electronics for a wide range of detector applications. Since commercial CMOS processes ...maintain a steady trend in device scaling, it is essential to monitor the impact of these technological advances on the noise parameters of the devices. In this paper we present the results of an extensive analysis carried out on CMOS transistors fabricated in 0.35, 0.25, and 0.18 mum technologies from different foundries. This allows us to evaluate the behavior of 1/f and channel thermal noise parameters with different gate oxide thickness and minimum channel length and to give an estimate of their process-to-process spread. The experimental analysis is focused on actual device operating conditions in monolithic detector readout systems. This means that moderate or weak inversion are often the only relevant regions for front-end devices. To account for different detector requirements, the noise behavior of devices with different geometries and input capacitance was investigated. The large set of data gathered from the measurements provides a powerful tool to model noise parameters and establish front-end design criteria in deep submicrometer CMOS processes
High-density high-speed CMOS and BiCMOS technologies are today widely used for the design of readout integrated circuits for room-temperature X- and /spl gamma/-ray imaging detectors. This paper ...describes a laboratory instrument that was developed to characterize the noise performances of CMOS devices to be used for high-speed analog signal processing. This instrument extends the noise-measuring capabilities beyond 100 MHz to detect the white noise component beyond the 1/f noise corner frequency, which in shorter channel devices shifts to higher values as compared to long-channel transistors.
This paper is motivated by the growing interest of the detector and readout electronics community towards silicon-on-insulator CMOS processes. Advanced SOI MOSFETs feature peculiar electrical ...characteristics impacting their performance with respect to bulk CMOS devices. Here we mainly focus on the study of these effects on the noise parameters of the transistors, using experimental data relevant to 180 nm fully depleted SOI devices as a reference. The comparison in terms of white and 1/f noise components with bulk MOSFETs with the same minimum feature size gives a basis of estimate for the signal-to-noise ratio achievable in detector front-end integrated circuits designed in an SOI technology.
During the past 15 years, the CMOS technologies have provided the most widely followed approach to signal processing with microstrip detectors. In more recent times, CMOS front-end systems have been ...developed to acquire and process signals from pixel detectors. During the past few years, the favor toward CMOS processes in their applications in the broad area of detector signal processing has been enhanced by the technological advancement known as
device scaling and by two aspects connected to it. One is the shrinking in channel length
L into the deep submicron region. The second one is the related reduction in the gate-oxide thickness
t
ox to a few nm. The reduction in
t
ox has, as a consequence of primary importance, a decreased 1/
f-noise contribution to the equivalent noise charge (ENC). The thinner gate-oxide and the shrinking in gate length, in some regions of operations, concur to increase the transconductance of the device, which results in a smaller ENC contribution from channel thermal noise. The goal of the present paper is to address the question of whether or not the most advanced CMOS processes may meet the requirements set by high resolution, high dynamic range applications like the energy-dispersive photon analysis with solid-state detectors of comparatively large capacitance.
A chip has been developed for reading out the silicon strip detectors in the new BTeV colliding beam experiment at Fermilab. The chip has been designed in a 0.25 /spl mu/m complementary ...metal-oxide-semiconductor (CMOS) technology for high radiation tolerance. Numerous programmable features have been added to the chip, such as setup for operation at different beam crossing intervals. A full size chip has been fabricated and successfully tested. The design philosophy, circuit features, and test results are presented in this paper.
This paper presents a study of the noise behavior of deep submicron CMOS transistors, in view of applications to analog front-end systems for high granularity detectors. The white component of the ...noise voltage spectrum, which is most important for fast signal processing, and the 1/
f noise contribution are investigated to find low-noise design criteria concerning the choice of the polarity and of the channel length of the preamplifier input device in low-power operating conditions. This analysis is supported by experimental data from noise measurements on CMOS devices belonging to a
0.35
μm
process.
The results discussed in this paper are relevant to junction field effect transistors (JFETs) and JFET-based charge sensitive amplifiers fabricated in a detector compatible process. Such structures ...were irradiated with 27 MeV protons to evaluate the suitability of the technology for space applications and high-energy physics experiments from the standpoint of radiation tolerance. The process investigated in this work, originally designed for the fabrication of silicon detectors to be operated in a fully depleted condition, has been tuned to embed N-channel JFETs, NMOS devices and bipolar transistors in the same high resistivity substrate. The most significant electrical parameters have been monitored after exposing the test structures to different proton fluences in order to characterize their total dose and bulk damage response. Comparison with the results from previous irradiations with /spl gamma/-rays might be helpful in shedding light on the fundamental mechanisms underlying radiation damage in JFET silicon devices.
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