This work presents a sub-μW on-chip oscillator for fully integrated system-on-chip designs. The proposed oscillator introduces a resistive frequency locked loop topology for accurate clock ...generation. In this topology, a switched-capacitor circuit is controlled by an internal voltage-controlled oscillator (VCO), and the equivalent resistance of this switched-capacitor is matched to a temperature-compensated on-chip resistor using an ultra-low power amplifier. This design yields a temperature-compensated frequency from the internal VCO. The approach eliminates the traditional comparator from the oscillation loop; this comparator typically consumes a significant portion of the total oscillator power and limits temperature stability in conventional RC relaxation oscillators due to its temperature-dependent delay. A test chip is fabricated in 0.18 μm CMOS that exhibits a temperature coefficient of 34.3 ppm/°C with long-term stability of less than 7 ppm (12 second integration time) while consuming 110 nW at 70.4 kHz. A radio transmitter circuit that uses the proposed oscillator as a baseband timing source is also presented to demonstrate a system-on-chip design using this oscillator.
This paper presents a fully integrated energy harvester that maintains >35% end-to-end efficiency when harvesting from a 0.84 mm 2 solar cell in low light condition of 260 lux, converting 7 nW input ...power from 250 mV to 4 V. Newly proposed self-oscillating switched-capacitor (SC) DC-DC voltage doublers are cascaded to form a complete harvester, with configurable overall conversion ratio from 9× to 23×. In each voltage doubler, the oscillator is completely internalized within the SC network, eliminating clock generation and level shifting power overheads. A single doubler has >70% measured efficiency across 1 nA to 0.35 mA output current ( >10 5 range) with low idle power consumption of 170 pW. In the harvester, each doubler has independent frequency modulation to maintain its optimum conversion efficiency, enabling optimization of harvester overall conversion efficiency. A leakage-based delay element provides energy-efficient frequency control over a wide range, enabling low idle power consumption and a wide load range with optimum conversion efficiency. The harvester delivers 5 nW-5 μW output power with >40% efficiency and has an idle power consumption 3 nW, in test chip fabricated in 0.18 μm CMOS technology.
This paper presents a new energy-efficient ring oscillator collapse-based comparator, named edge-pursuit comparator (EPC). This comparator automatically adjusts the performance by changing the ...comparison energy according to its input difference without any control, eliminating unnecessary energy spent on coarse comparisons. Furthermore, a detailed analysis of the EPC in the phase domain shows improved energy efficiency over conventional comparators even without energy scaling, and wider resolution tuning capability with small load capacitance and area. The EPC is used in a successive-approximation-register analog-to-digital converter (SAR ADC) design, which supplements a 10 b differential coarse capacitive digital-to-analog converter (CDAC) with a 5 b common-mode CDAC. This offers an additional 5 b of resolution with common mode to differential gain tuning that improves linearity by reducing the effect of switch parasitic capacitance. A test chip fabricated in 40 nm CMOS shows 74.12 dB signal-to-noise and distortion ratio and 173.4 dB Schreier Figure-of-Merit. With the full ADC consuming 1.17 μW, the comparator consumes 104 nW, which is only 8.9% of the full ADC power, proving the comparator's energy efficiency.
In this work, a switched-capacitor voltage regulator (SCVR) that dithers flying capacitance to reduce output voltage ripple is presented, and the benefits of such ripple reduction are investigated. ...In the proposed technique, SC converters are designed to run at the maximum available frequency, and the flying capacitance for different phases is adjusted according to load current change through comparators and a digital controller. The proposed technique is demonstrated in a 65 nm test chip consisting of a 40-phase SCVR with 4b capacitance modulation (CM) and a 2:1 conversion ratio. On-chip circuits for ripple measurement and load performance monitoring were included to accurately assess the magnitude and impact of ripple reduction. Measurement results show that at a 2.3 V input, an on-chip ripple magnitude of 6-16 mV at 1 V output is achieved for 11-142 mA load. Peak efficiency is 70.8% at a power density of 0.187 W/mm 2 .
A self-sustainable sensing platform powered entirely by small-scale benthic microbial fuel cells (MFCs) for oceanic sensing applications is presented. An ultra-low power chip featuring an ARM ...Cortex-M0 processor, 3 kB of SRAM, and power management unit (PMU) is designed to consume 11 nW in sleep mode for perpetual sensing operation. The PMU includes a switched-capacitor DC/DC converter designed for efficient energy harvesting and step-down conversion for a wide range of input and output power. A small-scale MFC with 21.3 cm 2 anode surface area was connected to the PMU to charge a thin-film battery of 1 mAh capacity. A 49.3-hour long-term experiment with 8-min sleep interval and 1-s wake-up time demonstrated the sustainability of system-on-mud concept. During sleep mode operation, the system charges the 4 V battery at 380 nA from the micro-MFC generating 5.4 μW of power, which allows up to 20 mA of active mode current with net energy neutrality.
Ultra-low power microsystems are gaining more popularity due to their applicability in critical areas of societal need. Power management in these microsystems is a major challenge as a relatively ...high battery voltage (e.g., 4V) must be down-converted to several low supplies, such as 0.6V for near-threshold digital circuits and 1.2V for analog circuits 1. Furthermore, the small form factors of such systems rule out the use of external inductors, making switched-capacitor (SC) DC-DC converters the favored topology 2-4.
Integrated LDOs cost-effectively enable fine-grain voltage regulation for digital IP blocks. A distributed LDO architecture, where a number of dispersed LDO units supply a single domain with shared ...power delivery network (PDN), has been recently proposed for point-of-load regulation improving both local IR-drop and transient droop response across the IP domain 1-3. However, previous distributed LDOs used custom communication between a global controller and local distributed LDO controllers 1, custom communication between neighboring LDO controllers 2, and/or analog voltage sensors with associated shared \mathrm{V}_{\mathrm{REF}} generation and routing 1-3. This paper presents a fully synthesizable, Distributed, and scalable all-Digital LDO (D-DLDO) voltage regulator (Fig. 25.1.1) with the following salient features: (1) fast single-cycle voltage monitoring using a Digital Supply-Voltage Sensor (DSVS), (2) fast digital PID-based controller, and (3) APR-friendly and tile-able design without the need to generate or route any global or inter-LDO digital/analog signals. A test-chip is implemented with 9 DLDO units in 10nm CMOS (Fig. 25.1.7). Each DLDO unit, including its power gates (PGs), DSVS, and controller, was fully synthesized using standard library cells and industry-standard automatic placement-and-routing (APR) tools.
This paper presents a novel reset scheme for mm-scale sensing systems with stringent volume and area constraints. In such systems, multi-layer structure is required to maximize the silicon area per ...volume and minimize the system size. The multi-layer structure requires wirebonding connections for power delivery and communication among layers, but the area overhead for wirebonding pads can be significant. The proposed reset scheme exploits already existing power wires and thus does not require additional wires for system-wide reset operation. To implement the proposed reset scheme, a power management unit is designed to impose reset condition, and a reset detector is designed to interpret the reset condition indicated by the power wires. The reset detector uses a coupling capacitor for the initial power-up and a feedback path to hold the developed supply voltage. The prototype reset detector is fabricated in a 180-μm CMOS process, and the measurement results with the prototype mm-scale system confirmed robust reset operation over a wide range of temperatures and voltages. KCI Citation Count: 1
Visual monitoring with CMOS image sensors opens up a variety of new applications for wireless sensor nodes, ranging from military surveillance to in vivo molecular imaging. In particular, the ability ...to detect motion can enable more intelligent power management through on-demand duty cycling and reduced data-retention requirements. Conventional imager designs focus on achieving higher resolution, frame rate 1, or dynamic range 2, resulting in power consumption levels that are unsuitable for battery-powered wireless sensor nodes 3.
A 1.0 mm 3 general-purpose sensor node platform with heterogeneous multi-layer structure is proposed. The sensor platform benefits from modularity by allowing the addition/removal of IC layers. A new ...low power I 2 C interface is introduced for energy efficient inter-layer communication with compatibility to commercial I 2 C protocols. A self-adapting power management unit is proposed for efficient battery voltage down conversion for wide range of battery voltages and load current. The power management unit also adapts itself by monitoring energy harvesting conditions and harvesting sources and is capable of harvesting from solar, thermal and microbial fuel cells. An optical wakeup receiver is proposed for sensor node programming and synchronization with 228 pW standby power. The system also includes two processors, timer, temperature sensor, and low-power imager. Standby power of the system is 11 nW.
