Second-level trigger in the Pierre Auger Fluorescence Detector Szadkowski, Zbigniew
Nuclear instruments & methods in physics research. Section A, Accelerators, spectrometers, detectors and associated equipment,
06/2001, Letnik:
465, Številka:
2
Journal Article
Recenzirano
The development and design of the second-level trigger for Fluorescence Detector in the Pierre Auger Experiment implemented in VLSI Altera FPGA chips is presented. Results show that Altera chip is a ...very good choice for sophisticated projects ensuring low propagation time, flexibility and sufficient capacity.
The surface detector array of the Pierre Auger Observatory comprises 1600 water Cherenkov detectors distributed over an area of 3000km2. The Cherenkov light is detected by three 9-in. ...photo-multiplier tubes from which the signals of the anode and last dynode are digitized by 10bit 40MHz FADCs. An Altera Cyclone FPGA is employed to generate different local triggers and to handle the data transfer to a communication board. After briefly discussing the design of the cards we present an autonomous test-bench, which has been set up in order to test the large number of boards prior to installation in the field. The qualification procedure and the results obtained in the laboratory are presented. Up to three years of operation in the field demonstrate a very good performance and reliability of the Front-End cards.
The development of a new first level trigger for the surface array in the Pierre Auger Observatory is described. It utilizes the new Altera
®
family Cyclone
TM which is available since March 2003. ...Different from previous and the currently used design based on the APEX
TM and ACEX
®
families, respectively, it offers much higher capacity of logic registers and memories, a simplified board design, lower power consumption, and lower cost. The paper describes the board design, internal structures of the programming routines, various trigger implementations and test results obtained in the laboratory.
The Pierre Auger Observatory surface array will contain 1600 surface detector stations distributed over 3000 km/sup 2/ on each Southern (Argentina, under construction since 2000) and Northern Site ...(Utah, planned to be built since 2005). The large area covered, the limited power budget necessitated by solar power operation, the restricted data bandwidth available through the stations' wireless network connections, and the temperature extremes inherent in an uncontrolled environment, impose special constraints on the surface detector trigger system. Several approaches to the implementation of the first level trigger were pursued during the engineering phase of the project in the lab and in the field. In this paper the Programmable Logic Devices (PLD) solutions, based upon industrial grade Altera/spl reg/ APEX/spl trade/, ACEX/spl reg/, Cyclone/spl trade/ series are presented. The APEX/spl trade/ design is working successfully on the Engineering Array since December 2000. The ACEX/spl reg/ cost-effective solution has been chosen for the final design, however the Cyclone/spl trade/ design, as the single chip solution with the best parameters, is still under investigation and is considered either as an improvement option for the Southern Site or as the baseline for the Northern Site.
For the observation of ultra high-energy cosmic rays (UHECRs) by the detection of their coherent radio emission an FPGA based wavelet trigger is being developed. Using radio detection, the ...electromagnetic part of an air shower in the atmosphere may be studied in detail, thus providing information complementary to that obtained by water Cherenkov detectors which are predominantly sensitive to the muonic content of an air shower at ground. For an extensive radio detector array, due to the limited communication data rate, a sophisticated self trigger is necessary. The wavelet trigger investigating online a power of signals is promising, however its implementation requires some optimizations. The digitized signals are converted from the time to frequency domain by a 32-point FFT procedure, then multiplied by wavelet transforms. Altera ® FFT routines convert ADC data as blocks of 2 N samples. FFT coefficients are provided in a serial stream in 2 time bins. An estimated signals power strongly depends on relatively positions of the FFT(data) and the wavelet transforms in a frequency domain. Additional procedure has to calculate a most efficient selection of the sample block to reach a response corresponding to a maximal signal power. If a set of FFT coefficients were available in each clock cycle, the signal power could be estimated also in each clock cycle and additional tuning procedure would not be necessary. The paper describes an implementation of the 32-point FFT algorithm into Altera ® FPGA providing all 32 complex DFT coefficients for the wavelet trigger in each clock cycle as well as a resource occupancy, timing and a power consumption for several variants implementing up to 12 wavelet engines. Measurements on an Altera ® 's development kit fully confirmed our expectation based on simulated configurations. The presented results give a green light for a development of the Front-End Board prototype based on the newest Cyclone ® V FPGA with the wavelet trigger for radio detection of cosmic rays.
The DCT trigger allows recognition of ADC traces with a very short rise time and fast exponential attenuation related to a narrow, flat muon component of very inclined extensive air showers generated ...by hadrons and starting their development early in the atmosphere. Showers, crossing a surface detector composed of water Cherenkow tanks, such as in the Pierre Auger Observatory, generate Cherenkov light, which may hit PMTs directly or after several reflections. The geometry of the water Cherenkov tank composes a type of the filter prefering a detection of very inclined showers (with very large zenith angle), where mainly two PMTs can be hit by direct light. The 3rd PMT is next hit by reflected light, but with some delay. By fast sampling (80 MHz) this delay gives signal in the next time bin. Two-fold coincidences of DCT coefficients allow triggering signals currently being ignored due to either too high amplitude threshold or due to their de-synchronization in time causing a tank geometry. Three DCT engines implemented into EP3C40F324I7 FPGA used all DSP blocks generate the spectral trigger, when in at least 2 channels 8 DCT coefficients simultaneously are inside the acceptance lane. Additional veto signal (analyzing the amplitude) controls a trigger rate to avoid a saturation of a transmission channel. Both lab and long-term field measurements on the test tank confirm a high efficiency of the recognition of expected patterns of ADC traces.
The paper describes the prototype of the Master/Slave (a water Cherenkov surface detector triggers the underground muon counters) synchronous data acquisition system with 80/320 MHz sampling in the ...surface/underground segments built on unified Altera ® platform - CycloneIII/CycloneIV ® FPGAs with implemented NIOS ® processors in each segment. NIOS ® processors eliminate external micro-controllers and allow generating necessary interfaces: SDRAM controller, UART, SPI, DMA, previously implemented from logic elements. Moving several slow tasks from the logic block (coding in the AHDL) to the NIOS ® (coding in C) dramatically simplifies the system and increases its flexibility. A time margin for all processes managing by the soft-core NIOS ® for the 100 Hz T1 trigger rate remains sufficient. Splitting 64 input channel just after fast input FPGA registers clocked by 320 MHz into 128-bit bus with twice lower clock allows achieving global registered performance of 160 MHz for the entire trigger/memory circuitry. NIOS ® processors communicate each other via UART protocol and RS485 standard. Underground CycloneIV ® FPGA is programmed remotely via additional MAXII CPLD with non-volatile programming memory. Tests have showed that a full synchronous cycle: a transfer of the trigger with a time stamp from the surface detector into the underground segment via a dedicated line with a galvanic barrier, freezing data from 64 channels at 320 MHz sampling in an internal DPRAMs, writing/reading data into/from external SDRAM, extraction physical data identified by sent from Central Data Acquisition System (CDAS) GPS time stamps and its transfer from the underground NIOS ® via surface NIOS ® to CDAS, is successful.
For the observation of ultra high-energy cosmic rays (UHECRs) by the detection of their coherent radio emission an FPGA based wavelet trigger is being developed. Using radio detection, the ...electromagnetic part of an air shower in the atmosphere may be studied in detail, thus providing information complementary to that obtained by water Cherenkov detectors which are predominantly sensitive to the muonic content of an air shower at ground. For an extensive radio detector array, due to the limited communication data rate, a sophisticated self trigger is necessary. The wavelet trigger investigating online a power of signals is promising, however its implementation requires some optimizations. The digitized signals are converted from the time to frequency domain by a standard Altera ® library based FFT procedure, then multiplied by wavelet transforms and finally converted to the time-domain again. Altera ® FFT routines convert ADC data as blocks of 2 N samples. FFT coefficients are provided in a serial stream in 2 N time bins. An estimated signals power strongly depends on relatively positions of the FFT(data) and the wavelet transforms in a frequency domain. Additional procedure has to calculate a most efficient selection of the sample block to reach a response corresponding to a maximal signal power. If a set of FFT coefficients were available in each clock cycle, the signal power could be estimated also in each clock cycle and additional tuning procedure would not be necessary. The paper describes an implementation of the 32-point FFT algorithm into Altera ® FPGA providing all 32 complex DFT coefficients for the wavelet trigger.
The surface detector array of the Pierre Auger Observatory contain 1600 water Cherenkov detectors spread over an area of 3000 km 2 . The Cherenkov light is detected by three 9-inch photomultiplier ...tubes from which the signals of the anode and last dynode are digitized by 10 bit ADCs. The currently used generations of the Front-End Boards equipped with the ACEX ® and Cyclone™ chips were sampled with 40 MHz clock. New requirements from the Auger North (100 MHz) and AMIGA (80 MHz) specification as well as proposal of new spectral triggers based on the 16-point Discrete Cosine Transform (DCT) requires a new Front End Boards with more powerful FPGA chip. The DCT trigger can be only implemented in a newer FPGA chips supported by sufficient amount of DSP blocks. The DCT trigger allows recognition of ADC traces with a very short rise time and fast exponential attenuation related to a narrow, flat muon component of very inclined extensive air showers generated by hadrons and starting their development early in the atmosphere. The DCT based on only real coefficients in the frequency domain, provides much more sensitive trigger conditions and a simpler interpretation in comparison to a discrete Fourier transform (DFT) that is based on complex coefficients. It also offers a scaling feature. The ratio of the DCT coefficients to the 1 st harmonics depends only on the shape of signals, not on their amplitudes. 10 prototype boards equipped with Altera ® CycloneIII™ FPGA have been fabricated and successively tested in the lab and in real pampas conditions in six test surface detectors within April 19 - July 26, 2009. Boards contain only a single FPGA chip, which implements also the slow channel, in previous three generations supported by the external Dual-Port RAM. Tests confirmed full stability and high reliability of the digital part. Both lab and field tests confirm a high efficiency of the recognition of expected patterns of ADC traces.
