In this work, the issue of abnormal two-stage hot carrier injection (HCI) degradation in n-type lateral double-diffused MOS (LDMOS) transistors is explored. The degradation mechanism is divided into ...two stages. The first stage is the electron injection into the interface layer (IL) caused by the impact ionization that occurs under the contact field plate (CFP), resulting in the degradation of the ON-current (<inline-formula> <tex-math notation="LaTeX">\textit{I}_{\text{on}}\text{)}</tex-math> </inline-formula>. The second stage of deterioration is the positive bias temperature instability (PBTI) effects caused by Joule heating, which leads to defects in the SiO<inline-formula> <tex-math notation="LaTeX">_{\text{2}}</tex-math> </inline-formula>/Si interface, and injects electrons in the channel into SiO<inline-formula> <tex-math notation="LaTeX">_{\text{2}}</tex-math> </inline-formula>, which increases the subthreshold swing (S.S) of the device and causes the threshold voltage (<inline-formula> <tex-math notation="LaTeX">\textit{V}_{\text{th}}\text{)}</tex-math> </inline-formula> to shift. It has been proved by temperature variation experiments and technology computer-aided design (TCAD) simulations that HCI will indeed produce severe PBTI effects and lead to device degradation during long-term HCI.
In this work, the impact of positive bias stress (PBS) on an all copper(Cu)-electrode a-InGaZnO TFT is discussed. Commonly, Cu diffusion from the source/drain electrode after negative bias stress ...(NBS) leads to degradations in the on-state current and subthreshold swing. However, this study finds that diffusion in the gate insulator layer from the gate electrode suffers from more serious degradation. Eventually, this phenomenon causes a serious breakdown of the gate insulator such that it loses the transistor function. Results indicate that after 2000s of PBS, accumulation of Cu ions forms a filament which dominates the leakage path. During the stress duration, the gate leakage current is monitored and current fittings are adopted to confirm the phenomena. Furthermore, temperature dependencies have verified the results of hopping and Ohmic conduction at different stages of deterioration. Compared to previous literature that focus on the impacts of source/drain electrodes, this work suggests that gate engineering for thin film transistors is more urgent for high-quality display applications.
In this experiment, the electrical performance of zinc oxide based-resistive random access memory (RRAM) is successfully improved by using annealing in ammonia hydroxide solution at low-temperature ...and high pressure to complete ammonium-doped ZnO based-RRAM. The results of material analysis indicate that using CO 2 as ammonia hydroxide carrier during the annealing process leads to the reduction in dangling bond density. This can be clearly observed in the decrease in breakdown voltage during the forming process and a lower operating current during operation. Furthermore, in this ammonium-doped ZnO based-RRAM, we study the molecular doping of NH 3 in ZnO, where the endurance and retention properties are improved as well. These improvements can be attributed to the higher concentration of nitrogen in the switching layer, which can effectively control the active oxygen ions during the operation process.
In this work, degradation due to carrier injection at the etch-stop layer was observed under dynamic switching. A significant threshold voltage shift is observed in alternating current stress but is ...absent in direct current stress. A model which transitions from the accumulation to depletion phases indicates electron-trapping at the etch-stop layer since the transition time is insufficient for carriers to drift back to the source/drain electrodes. Results are discussed through both horizontal and lateral band diagrams to confirm back channel injections. Also, comparing transfer curves with capacitance-voltage curves at the same threshold voltage in different structure devices provides direct evidence of electron-trapping regions. Finally, COMSOL simulation is performed to confirm the difference in electron-trapping between back channel and corner regions, a difference which leads to an abnormal hump during capacitance-voltage measurements.
Anomalous drain-induced barrier lowering (DIBL) is observed in n-type low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs) with a full light shield (LS) structure. Drain current ...versus gate voltage curves exhibit a threshold voltage (V TH ) shift and hump effect as the drain bias increases, and demonstrate the unsaturated output property. Because of the inherent grain boundary and grain protrusion of LTPS TFTs, considerable impact ionization occurs, thus generating electron-hole pairs when operated at high current, leading to a floating body effect, that confers the occurrence of the kink effect. However, the unsaturated current characteristic is induced by the LS because of its coupling potential of the LS. Therefore, partitioned LS structures are proposed to further improve the DIBL and weak the kink effect.
In this work, an abnormal lowering of subthreshold swing (SS) after self-heating stress in a device with thick channel is observed. A model of interface defect shielding is proposed, based on ...electron trapping at the channel/gate insulator interface. The phenomenon is discussed systematically through the band diagram and extractions of the field effective mobility. Results suggest that a depletion region appears after electron trapping at the front channel, which then prevents the carriers from reaching the interface defects. Therefore, an abnormal superior electrical performance after stress is observed. Finally, a dual gate amorphous InGaZnO (a-IGZO) thin film transistor (TFT) is used to clarify the phenomenon. Results from different top gate bias voltage confirms the bulk accumulation and better gate control.
In this article, an n-type double-gate low-temperature polysilicon (LTPS) TFT is investigated. Previous work has confirmed that the hot-carrier effect will cause impact ionization. Here we observed ...that, after hot-carrier stress (HCS), the transfer curve in the saturation region has a negative <inline-formula> <tex-math notation="LaTeX">\text{V}_{\mathrm {th}} </tex-math></inline-formula> shift, and a hump is also observed. The reverse output characteristic shows that gate induced drain leakage (GIDL) of the transistor gradually increases and the subthreshold swing (S.S.) has a tendency to collapse. In structures with longer lightly doped drain (LDD) lengths, the electric field at both source/drain side can be effectively dispersed. Thereby, an extended LDD can reduce the overall degradation, and a physical model of explanation is proposed. By using the energy band diagram, we clarify how the additional electron hole pairs affect the output property. Next, Silvaco TCAD simulation is utilized to illustrate the electric field distribution and validate the physical model.
The instability of amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistors (TFTs) under ultraviolet (UV) light was thoroughly investigated in this paper. Unlike in a darkened state, an ...off-state leakage current can be found in the dual-sweep I-V transfer curve of a-IGZO TFTs under UV light illumination. Furthermore, despite the same UV light condition, the forward sweep and reverse sweep show different I-V curves, representing two different physical mechanisms. First, the subthreshold swing degradation and threshold voltage shift to the negative direction in the forward sweep are due to the total channel barrier lowering and can be confirmed by changing the light exposure region. Second, in the reverse sweep, the suggested back-channel leakage current can be controlled by dual-gate TFTs. UV light exposure of the metal-insulator-semiconductor-metal structure verifies that the off-state leakage current passes through the back channel in a reverse sweep. Finally, the physical mechanism links between forward and reverse sweeps have comprehensive interpretation in this paper.
Abstract
This study examines self-heating-related instability in n-channel low-temperature polysilicon thin-film transistors with different source/drain contact hole densities. Devices with more ...contact holes exhibit a higher on-current without additional parasitic capacitance, further enhancing the RC delay property. For high-current-induced self-heating stress, a device with one contact hole has one hump due to the kink effect. However, a device with six contact holes has two humps, induced by the kink effect and thermionic field emission. COMSOL simulations of heat distribution and energy bands are performed to examine the different degradation behaviors, and then physical models are proposed.
Degradation in low-temperature polycrystalline-silicon thin-film transistors after electrical stress was thoroughly investigated in this work. Main channel degradation, abnormal hump generation and ...hysteresis appearing in the hump region can be observed after positive bias stress. Furthermore, the difference in subthreshold swing (SS) values between forward/reverse sweep is observed. The electron trapping into the gate insulator (GI) dominates the main degradation and the hump generation. Additionally, the difference in SS values which appears in the hump region is attributed to the interface traps and the hysteresis is caused by electron trapping/detrapping into GI.
