In this study, negative gate bias stress (NGBS) is applied to the Si3N4 metal-insulator-semiconductor high electron mobility transistors (MIS-HEMTs). The gate electron injected into the Si3N4 ...dielectric layer and the holes generated by the impact ionization trapped into the AlGaN layer are the two main degradation mechanisms, which cause the unstable threshold voltage. Moreover, it is discovered that an abnormal <inline-formula> <tex-math notation="LaTeX">{C} </tex-math></inline-formula>-<inline-formula> <tex-math notation="LaTeX">{V} </tex-math></inline-formula> hump is generated after NGBS because of the uneven hole trapping at the AlGaN near the channel under the gate. The unusual direction of the electric field, which is related to the mesa isolation technology, is observed under NGBS condition in the Silvaco TCAD simulation. The location of the hole trapping is verified by the positive gate bias after NGBS during the recovery time. Finally, the device without the mesa isolation is used to verify the abnormal degradation results.
The instability of amorphous indiu–galliu–zinc oxide (a-IGZO) thin-film transistors (TFTs) under ultraviolet (UV) light was thoroughly investigated in this paper. Unlike in a darkened state, an ...off-state leakage current can be found in the dual-sweep I–V transfer curve of a-IGZO TFTs under UV light illumination. Furthermore, despite the same UV light condition, the forward sweep and reverse sweep show different I–V curves, representing two different physical mechanisms. First, the subthreshold swing degradation and threshold voltage shift to the negative direction in the forward sweep are due to the total channel barrier lowering and can be confirmed by changing the light exposure region. Second, in the reverse sweep, the suggested back-channel leakage current can be controlled by dual-gate TFTs. UV light exposure of the metal–insulator–semiconductor–metal structure verifies that the off-state leakage current passes through the back channel in a reverse sweep. Finally, the physical mechanism links between forward and reverse sweeps have comprehensive interpretation in this paper.
In this work, an opposite sub-threshold swing trend of I-curve to C-V curve in tri-layer IGZO TFT is observed. Thermal and electrical field effects during stress duration is investigated to clarify ...this behavior. Results indicate a carrier distribution migration phenomenon; carriers are away from the gate insulator surface after self-heating stress which is caused by defect generations at channel/GI interface. Since carrier tends to locate at the middle layer (In-rich layer) after self-heating stress, carriers away from surface defects leads to a better subthreshold swing in I-V curve. However, C-V curves detects the information of defects leading to S.S degradation.
In this work, Indium-Gallium-Zinc-Oxide Thin Film Transistors (IGZO-TFTs) with different channel thickness has been compared after self-heating stress (SHS). Although TFTs with a larger channel ...thickness possess a greater current during stress durations, a less degradation is observed. From results, the threshold voltage shift in the transfer characteristics is well described by the stretched-exponential equation. Also, the average effective barrier height, Eτ, is extracted to compare the degradation difference between both components. Accordingly, the barrier height in the thick channel layer component is twice of that in the thin channel layer component. Finally, COMSOL simulation is given to demonstrate the electrical difference at the gate insulator layer to confirm such phenomenon.
Abstract
UV‐sensing devices have received significant recent attention for applications in areas such as human health, fire detection, and optical communication. One key factor for product ...commercialization is determining the optimal materials that allow for integration of excellent UV‐sensing properties with compatibility with industrial fabrication processes. However, current UV sensors often fail to achieve this due to either mismatched materials or a device that must be excessively large in order to produce enough photocurrent for UV detection. The UV‐light‐sensing properties of an amorphous InGaZnO
4
(IGZO) thin‐film transistor with a dual‐gate structure and relatively small device size (width/length = 50 µm/10 µm) that achieves high sensitivity through a threshold‐voltage‐(
V
th
)‐adjustment method is proposed. Comparing the drain currents under UV exposure to those under darkened conditions indicates that the ratio between the photoinduced and dark current reaches 10
6
. Furthermore, the UV sensitivity of the dual‐gate transistors can be adjusted by varying the bottom gate voltage, with each pixel of the sensor then being read out separately via scan line pulses. This allows the dual‐gate a‐IGZO transistor to be used for high‐performance UV sensing while being effectively integrated in display applications.
In this work, three MISHEMT devices with different electric-field-dispersion layer (EDL) behave the same pristine electrical properties. EDL, which is low dielectric constant (low-k), can effectively ...disperse electric field, which enhances breakdown voltage and improves reliability in MISHEMT. In a comparison of devices with high-k and low-k EDL, the on-state current (<inline-formula> <tex-math notation="LaTeX">\text{I}_{\mathrm{ on}} </tex-math></inline-formula>) of the high-k EDL devices is more significantly reduced than low-k EDL devices after off-state stress. A model for the dispersion of electric fields by the EDL is proposed for this interesting phenomenon. The distribution of the electric field is verified by Silvaco electric field simulation. Finally, the breakdown voltages of the three devices were measured, confirming that the devices with a low-k EDL can increase their breakdown voltages by an additional 600 V, which is 250 % higher than that in the high-k EDL device.
This paper demonstrates the cumulative effects of compressive stress and high current stress at high temperature in flexible a-InGaZnO 4 thin-film transistors. An abnormal hump can be found in the ...subthreshold regime in the results from a reliability test that combines high temperature and high current stress with mechanical bending at 10 mm. During this stress, holes will tend to inject into the defects in the etching stop layer near the source side, which is induced by compressive bending. A COMSOL simulation was performed and confirmed that defect generation occurs in the etching stop layer during compressive bending. Further, the path of the back-channel leakage current caused by the localized trapped holes was also confirmed by changing the width/length of thin film transistors (TFTs) in the reliability test. The precise hole trapping distribution was verified by a single side capacitance-voltage measurement and source/drain interchange measurement.
