Superconductor digital integrated circuits (ICs) require rapid evaluation of multiple copies to obtain statistical operational data. These data are used for assessing model-to-hardware correlation ...and facilitate iterative IC design development. The Integrated Cryogenic Electronics Testbed (ICE-T) is a cryogen-free test platform, which can test multiple chips simultaneously with similar convenience to a liquid-helium immersion probe and with cooldown times of between 3.3 to 4.5 hours. We have developed a three-chip insert to increase the volume of chip testing and demonstrated simultaneous cooling of six chips with two such inserts. We report the test statistics collected from 27 chips across a single wafer. We have also used the ICE-T's convenient temperature control system to evaluate chips in the 3.5 - 6 K range. Such evaluation determines the robustness of circuit design and its tolerance to critical current fluctuations due to fabrication variation.
Digital Channelizing Radio Frequency Receiver Gupta, D.; Filippov, T.V.; Kirichenko, A.F. ...
IEEE transactions on applied superconductivity,
06/2007, Letnik:
17, Številka:
2
Journal Article, Conference Proceeding
Recenzirano
HYPRES is developing a class of digital receivers featuring direct digitization at radio frequency (RF). Such a receiver consists of a wideband analog-to-digital converter (ADC) modulator and ...multiple digital channelizer units to extract different frequency bands-of-interest within the broad digitized spectrum. The single-bit oversampled data, from either a lowpass delta or bandpass delta-sigma modulator, are applied to one or more channelizers, each comprising digital in-phase and quadrature mixers and a pair of digital decimation filters. We perform channelization in two steps, the first at full ADC sampling clock frequency with rapid single flux quantum (RSFQ) digital circuits and the second at reduced (decimated) clock frequency with commercial field programmable gate array (FPGA) chips at room temperature. We have demonstrated lowpass and bandpass digital receivers by integrating an ADC modulator and a channelizer unit on the same chip at clock frequencies up to 20 GHz. These 1-cm 2 single-chip digital-RF receivers contain over 10,000 Josephson junctions. The channelizing receiver approach can be extended to include multiple ADC modulators and multiple channelizer units on a multi-chip module.
We describe several improvements that are being pursued to improve the dynamic range of lowpass phase modulation-demodulation (PMD) analog-to-digital converters (ADC). The existing ADC has been ...tested at sampling frequencies up to 29.44 GHz; a 89.15 dB signal to noise ratio (SNR) is achieved for a 10 MHz sinusoidal input, with the noise being measured in a reference 10 MHz bandwidth in the decimated band. The first improved approach involves a multi-rate ADC where the modulator sampling frequency is increased in multiples of the decimation filter clock. We have tested the multi-rate ADCs at sampling frequencies up to 46.08 GHz and 29.44 GHz for chips fabricated using the 4.5 and 1 kA/cm 2 fabrication processes respectively. For a single channel ADC, with a 9.92 MHz sinusoidal input, sampled at 29.44 GHz, the SNR is 83.93 dB in a reference 10 MHz bandwidth. The spur-free dynamic range (SFDR) is 95 dB. In another improved architecture, called the quarter-rate ADC, the modified quantizer quadruples the input dynamic range by distributing the input in a cyclical fashion to four output channels, each operating at a quarter of the fluxon transport rate. This enables quadrupling the synchronizer channels, providing an opportunity for up to 12 dB performance enhancement. A parallel counter following the multi-channel synchronizer converts the differential code to a multi-bit binary code, which is further processed by the decimation filter. A prototype version of this ADC with a two channel synchronizer, fabricated using the 4.5 kA/cm 2 process, has been tested up to a sampling frequency of 25.6 GHz. For a 10 MHz sinusoidal input, the SNR is 82.54 dB, with the noise measured in a reference 10 MHz bandwidth. We are also designing a subranging ADC with two PMD front-ends. Simulation results promise greater than 20 dB performance enhancement.
HYPRES has developed a high-resolution, dynamically programmable analog-to-digital converter (ADC) for radar and communications applications. The ADC uses the phase modulation-demodulation low-pass ...architecture and on-chip digital filtering. Detailed experimental results at 20 GHz clock frequency of the ADC chip fabricated with a 1 kA/cm 2 Nb process are presented and discussed. In addition to the standard ADC configuration, different ADC modifications are described. In the multi-rate ADC, the modulator sampling frequency is the twice the clock frequency for the time-interleaved digital filter. In addition to the standard parallel-output ADC, a serial output ADC and its interface to room temperature electronics are developed. This serial ADC chip fabricated with the advanced HYPRES 4.5 kA/cm 2 process operated up to 34 GHz clock. As a major step toward commercialization of superconducting electronics, an ADC chip was successfully packaged on a cryocooler where it showed reduced performance up to 11.52 GHz clock.
Superconductor Digital-RF Receiver Systems MUKHANOV, Oleg A.; KIRICHENKO, Dmitri; VERNIK, Igor V. ...
IEICE Transactions on Electronics,
03/2008, Letnik:
E91.C, Številka:
3
Journal Article
Recenzirano
Digital superconductor electronics has been experiencing rapid maturation with the emergence of smaller-scale, lower-cost communications applications which became the major technology drivers. These ...applications are primarily in the area of wireless communications, radar, and surveillance as well as in imaging and sensor systems. In these areas, the fundamental advantages of superconductivity translate into system benefits through novel Digital-RF architectures with direct digitization of wide band, high frequency radio frequency (RF) signals. At the same time the availability of relatively small 4K cryocoolers has lowered the foremost market barrier for cryogenically-cooled digital electronic systems. Recently, we have achieved a major breakthrough in the development, demonstration, and successful delivery of the cryocooled superconductor digital-RF receivers directly digitizing signals in a broad range from kilohertz to gigahertz. These essentially hybrid-technology systems combine a variety of superconductor and semiconductor technologies packaged with two-stage commercial cryocoolers: cryogenic Nb mixed-signal and digital circuits based on Rapid Single Flux Quantum (RSFQ) technology, room-temperature amplifiers, FPGA processing and control circuitry. The demonstrated cryocooled digital-RF systems are the world's first and fastest directly digitizing receivers operating with live satellite signals in X-band and performing signal acquisition in HF to L-band at ∼30GHz clock frequencies.
Modular, Multi-Function Digital-RF Receiver Systems Gupta, D; Kirichenko, D E; Dotsenko, V V ...
IEEE transactions on applied superconductivity,
06/2011, Letnik:
21, Številka:
3
Journal Article, Conference Proceeding
Recenzirano
Superconductor digital receiver systems of increasing functionality, modularity and user-friendliness have been developed. The modular design methodology ensures that within its input-output and heat ...load capacity, the system can be reconfigured to perform a different function by changing the chip module and by reprogramming FPGA-based digital signal processors. One of the systems (ADR-004), originally equipped with a 10 × 10 mm 2 channelizing receiver chip for signals intelligence application, was reconfigured with a 5 × 5 mm 2 1.1-GHz bandpass ADC chip to perform world's first multi-net Link-16 demonstration at a U.S. Navy facility. Substantial improvements in system integration have been obtained in each successive generation of digital-RF receiver systems. The latest (third) generation system (ADR-005), hosting a 5 × 5 mm 2 7.5-GHz bandpass ADC chip and an FPGA channelizer, successfully repeated the over-the-air SATCOM demonstration performed previously using a 1-cm 2 single-chip bandpass digital receiver with an on-chip superconductor channelizer. This system ran error-free for over 12 hours with and without a low-noise amplifier. To our knowledge, this is the first time an X-band SATCOM receiver has been operated without analog amplification and down-conversion in a military application.
Cosmic-ray tests of the DØ preshower detector Baringer, P; Bross, A; Buescher, V ...
Nuclear instruments & methods in physics research. Section A, Accelerators, spectrometers, detectors and associated equipment,
08/2001, Letnik:
469, Številka:
3
Journal Article
Recenzirano
Odprti dostop
The DØ preshower detector consists of scintillator strips with embedded wavelength-shifting fibers, and a readout using Visible Light Photon Counters. The response to minimum ionizing particles has ...been tested with cosmic-ray muons. We report results on the gain calibration and light-yield distributions. The spatial resolution is investigated taking into account the light sharing between strips, the effects of multiple scattering and various systematic uncertainties. The detection efficiency and noise contamination are also investigated.
Light emission from SiGe heterojunction bipolar transistors (HBTs) was characterized for photon emission microscopy applications. Radiative recombination dominates in the non-saturation regime. It ...increases in the saturation regime due to an increased concentration of minority charge carriers in the base. Hot electron radiation dominates in the avalanche and is suppressed at large collector currents due to base widening.
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