This paper presents a fully integrated energy harvester that maintains >35% end-to-end efficiency when harvesting from a 0.84 mm 2 solar cell in low light condition of 260 lux, converting 7 nW input ...power from 250 mV to 4 V. Newly proposed self-oscillating switched-capacitor (SC) DC-DC voltage doublers are cascaded to form a complete harvester, with configurable overall conversion ratio from 9× to 23×. In each voltage doubler, the oscillator is completely internalized within the SC network, eliminating clock generation and level shifting power overheads. A single doubler has >70% measured efficiency across 1 nA to 0.35 mA output current ( >10 5 range) with low idle power consumption of 170 pW. In the harvester, each doubler has independent frequency modulation to maintain its optimum conversion efficiency, enabling optimization of harvester overall conversion efficiency. A leakage-based delay element provides energy-efficient frequency control over a wide range, enabling low idle power consumption and a wide load range with optimum conversion efficiency. The harvester delivers 5 nW-5 μW output power with >40% efficiency and has an idle power consumption 3 nW, in test chip fabricated in 0.18 μm CMOS technology.
This paper presents a new energy-efficient ring oscillator collapse-based comparator, named edge-pursuit comparator (EPC). This comparator automatically adjusts the performance by changing the ...comparison energy according to its input difference without any control, eliminating unnecessary energy spent on coarse comparisons. Furthermore, a detailed analysis of the EPC in the phase domain shows improved energy efficiency over conventional comparators even without energy scaling, and wider resolution tuning capability with small load capacitance and area. The EPC is used in a successive-approximation-register analog-to-digital converter (SAR ADC) design, which supplements a 10 b differential coarse capacitive digital-to-analog converter (CDAC) with a 5 b common-mode CDAC. This offers an additional 5 b of resolution with common mode to differential gain tuning that improves linearity by reducing the effect of switch parasitic capacitance. A test chip fabricated in 40 nm CMOS shows 74.12 dB signal-to-noise and distortion ratio and 173.4 dB Schreier Figure-of-Merit. With the full ADC consuming 1.17 μW, the comparator consumes 104 nW, which is only 8.9% of the full ADC power, proving the comparator's energy efficiency.
A dual-slope capacitance-to-digital converter for pressure-sensing is presented and demonstrated in a complete microsystem. The design uses base capacitance subtraction with a configurable capacitor ...bank to narrow down input capacitance range and reduce conversion time. An energy-efficient iterative charge subtraction method is proposed, employing a current mirror that leverages the 3.6 V battery supply available in the system. We also propose dual-precision comparators to reduce comparator power while maintaining high accuracy during slope conversion, further improving energy efficiency. The converter occupies 0.105 mm 2 in 180 nm CMOS and achieves 44.2 dB SNR at 6.4 ms conversion time and 110 nW of power, corresponding to 5.3 pJ/conv-step FoM. The converter is integrated with a pressure transducer, battery, processor, power management unit, and radio to form a complete 1.4 mm × 2.8 mm × 1.6 mm pressure sensor system aimed at implantable devices. The multi-layer system is implemented in 180 nm CMOS. The system was tested for resolution in a pressure chamber with an external 3.6 V supply and serial communication bus, and the measured resolution of 0.77 mmHg was recorded. We also demonstrated the wireless readout of the pressure data on the stack system operating completely wirelessly using an integrated battery.
An automatically reconfigurable switched-capacitor DC-DC converter with multiple regulated outputs is presented for wireless-powered multi-unit implantable medical devices (IMDs). In such devices, ...the main controller unit is powered wirelessly and provides supply voltages to the circuits of the main unit as well as multiple connected sub-units. The proposed DC-DC converter simultaneously generates two regulated voltages for the main unit and two unregulated voltages for the sub-units, which have on-site low-dropout regulators. The converter consists of i) an input-adaptive DC-DC conversion stage with two switched-capacitor (SC) DC-DC converters in series and ii) a regulating stage. In the DC-DC conversion stage, the proposed converter automatically reconfigures the conversion ratio and connection order of the two SC DC-DC converters and selects the output nodes by load selection switches depending on the input level. Thanks to these adaptive configurations, the proposed converter offers high conversion efficiencies over a wide input voltage range even with fewer flying capacitors required for the reconfigurable conversion ratios. Moreover, the selection switches are reused to regulate the output voltages to desired levels, minimizing the overhead for subsequent regulation. The IC fabricated in a 180-nm standard CMOS process achieves a conversion efficiency of 95.5% for the unregulated voltages and up to 77.4% for the regulated voltages over a wide input range of 1 V to 4 V with 0.74-mV output ripple for a load current of 20 mA, while providing four outputs (2 regulated, 2 unregulated).
Owing to their high efficiency and high power density, hybrid DC-DC converters are gaining attention in academia and industry. However, no systematic procedure is currently available for creating new ...converter topologies where the number of inductors and capacitors are different. This paper proposes ConverGenT, an automated topological synthesis and analysis framework for two-phase hybrid DC-DC converters with one inductor, two capacitors consisting of one flying and one output capacitor. Consequently, all the converter topologies of this type are discovered. In contrast to the conventional approach that relies on intuition, this method requires less time and generates a complete set of converter topologies in a systematic manner. These two key advantages ensure that no possible converter topology is missed, making this method superior to the conventional approach. After generating a topology, all information about the converter topologies can be analyzed and verified manually or automatically, and the most suitable topology for a given application can be selected. ConverGenT has identified 62 converter families, each with a maximum of six topologies per family, that outperform conventional converters in certain aspects, with at least eight of these topologies having been published within the last five years. Details on topologies and performance of these converters are in the Appendix.
This brief presents a redundant-transition-free low-power flip-flop (FF), named contention-free change-sensing FF (C2SFF). The instability of a previous change-sensing circuit has been discovered ...under a test scenario where the data input change is uncorrelated with the clock signal. By resolving this instability, C2SFF is always contention-free and has low leakage, while maintaining low dynamic power by eliminating unnecessary transitions of internal clocked nodes. Without additional sizing efforts, C2SFF operates reliably down to 0.32V by removing all contention paths. Post-layout simulation results using a 65 nm CMOS process design kit show that the power consumption of C2SFF is reduced by 62.1%/52.8% with 10%/20% activity at 1V, and 56.9%/49.0% with 10%/20% activity at 0.4V, respectively, compared to transmission-gate FF (TGFF). In addition, C2SFF shows the second-best setup-hold window among tested FFs.
Capacitance sensors are widely used to measure various physical quantities, including position, pressure, and concentration of certain chemicals 1-6. Integrating capacitive sensors into a small ...wireless sensor system is challenging due to their large power consumption relative to the total system power/energy budget, which can be as low as a few nW 4. Typical capacitance-to-digital converters (CDCs) use charge sharing or charge transfer between capacitors to convert the sampled capacitance to voltage, which is then measured with an ADC 1-6. This approach requires complex analog circuits, such as amplifiers and ADCs, increasing design complexity and often increasing power consumption. Moreover, the initial capacitance to voltage conversion essentially limits the input capacitance range because of output voltage saturation. This paper presents a fully digital CDC that is based on the observation that when a ring oscillator (RO) is powered from a charged capacitance, the number of RO cycles required to discharge the capacitance to a fixed voltage is naturally linear with the capacitance value. This observation enables a simple, fully digital conversion scheme that is inherently linear. As a result, the proposed CDC performs conversion across a very wide capacitance range from 0.7pF to over 10nF with <; 0.06% linearity error. The CDC senses 11.3pF input capacitance with 35.1 pJ conversion energy and 141fJ/c-s FoM.
DRAM-based accelerators have shown their potential in addressing the memory wall challenge of the traditional von Neumann architecture. Such accelerators exploit charge sharing or logic circuits for ...simple logic operations. As a result, they require many cycles for more complex operations such as a multi-bit multiply-accumulate (MAC) operation, resulting in significant data access and movement and potentially worsening power efficiency.To overcome these limitations, this paper presents MAC-DO, an efficient and low-power DRAM-based accelerator. Compared to previous DRAM-based accelerators, a MAC-DO cell, consisting of two 1T1C DRAM cells, innately supports a multi-bit MAC operation within a single cycle, significantly improving power efficiency while maintaining good linearity and compatibility with existing 1T1C DRAM cell and array structures. This achievement is facilitated by a novel analog computation method utilizing charge steering. As a result, MAC-DO efficiently can accelerate convolutions based on output stationary mapping, supporting the majority of computations performed in deep neural networks.Our evaluation using transistor-level simulation shows that a test MAC-DO array with 16×16 MAC-DO cells achieves 120.96 TOPS/W and 97.07% Top-1 accuracy for MNIST dataset without retraining.
Near-threshold computing (NTC) is an attractive solution to stagnating energy efficiencies in digital integrated circuits, arising from slowed voltage scaling in nanometer CMOS 1-2. The design of ...sequential elements for NTC, as well as in voltage-scaled systems operating at both near-threshold and super-threshold, has not been extensively studied. However, it is well known that sequential elements have a strong sensitivity to process variations in NTC 2, which can have a significant impact on system yield and power consumption. In order to achieve reliable energy-efficient operation across a wide operating voltage range, a flip-flop should have the following attributes: 1) static operation, since dynamic nodes are highly susceptible to PVT variations at low voltage; 2) contention-free transitions, since ratioed logic has poor robustness across the wide range of device I ON /I OFF ratios incurred with voltage scaling; 3) single-phase clocking, which avoids toggling of internal clock inverters and the corresponding power penalty; 4) minimum or no area penalty compared to conventional flip-flops.
Recent low-power flip-flops (FFs) synthesize a signal (\boldsymbol{CKN}) that is activated only when the input data (\boldsymbol{D}) updates the output state (\boldsymbol{Q}) . It saves power ...consumption by avoiding unnecessary transitions in internal nodes. However, the circuit for \boldsymbol{CKN} that removes all redundant transitions becomes complex. As a result, its delay worsens timing parameters (setup time, hold time, \boldsymbol{CK}\_\boldsymbol{Q} delay) and the robustness of FFs too. By optimizing the delay of the clock insertion paths, the presented flip-flop (26TSPC) maximizes efficiency without speed degradation, while maintaining low hold time. Its design is based on 18TSPC, one of the fast and energy-efficient FFs, and its contention and redundant transition issues are also resolved. Post-layout simulation results based on 65 nm CMOS process show that 26TSPC consumes 83.9%/71.4% less power than that of conventional transmission-gate flop-flop (TGFF) with 10%/20% activity ratio at 1V and 75.4%/65.3% less power than that of TGFF with 10%/20% activity at 0.4V respectively. In addition, the hold time of 26TSPC is negative in all corners, featuring better timing reliability than other low-power FFs.
PDF
