Bayesian optimization is a promising methodology for analog circuit synthesis. However, the sequential nature of the Bayesian optimization framework significantly limits its ability to fully utilize ...real-world computational resources. In this article, we propose an efficient parallelizable Bayesian optimization algorithm via multiobjective acquisition function ensemble (MACE) to further accelerate the optimization procedure. By sampling query points from the Pareto front of the probability of improvement (PI), expected improvement (EI), and lower confidence bound (LCB), we combine the benefits of state-of-the-art acquisition functions to achieve a delicate tradeoff between exploration and exploitation for the unconstrained optimization problem. Based on this batch design, we further adjust the algorithm for the constrained optimization problem. By dividing the optimization procedure into two stages and first focusing on finding an initial feasible point, we manage to gain more information about the valid region and can better avoid sampling around the infeasible area. After achieving the first feasible point, we favor the feasible region by adopting a specially designed penalization term to the acquisition function ensemble. The experimental results quantitatively demonstrate that our proposed algorithm can reduce the overall simulation time by up to <inline-formula> <tex-math notation="LaTeX">74\times </tex-math></inline-formula> compared to differential evolution (DE) for the unconstrained optimization problem when the batch size is 15. For the constrained optimization problem, our proposed algorithm can speed up the optimization process by up to <inline-formula> <tex-math notation="LaTeX">15\times </tex-math></inline-formula> compared to the weighted EI-based Bayesian optimization (WEIBO) approach, when the batch size is 15.
The computation-intensive circuit simulation makes the analog circuit sizing challenging for large-scale/complicated analog/RF circuits. A Bayesian optimization approach has been proposed recently ...for the optimization problems involving the evaluations of black-box functions with high computational cost in either objective functions or constraints. In this paper, we propose a weighted expected improvement-based Bayesian optimization approach for automated analog circuit sizing. Gaussian processes (GP) are used as the online surrogate models for circuit performances. Expected improvement is selected as the acquisition function to balance the exploration and exploitation during the optimization procedure. The expected improvement is weighted by the probability of satisfying the constraints. In this paper, we propose a complete Bayesian optimization framework for the optimization of analog circuits with constraints for the first time. The existing GP model-based optimization methods for analog circuits take the GP models as either offline models or as assistance for the evolutionary algorithms. We also extend the Bayesian optimization algorithm to handle multi-objective optimization problems. Compared with the state-of-the-art approaches listed in this paper, the proposed Bayesian optimization method achieves better optimization results with significantly less number of simulations.
In this paper, a Bayesian optimization approach is proposed for yield optimization of analog and SRAM circuits. Gaussian process (GP) regression is employed to predict the yield over the design space ...with uncertainty information. An expected improvement acquisition function is constructed over the model and guides the optimization with a utility-based strategy. These techniques, as a whole, can significantly reduce the number of expensive yield estimations during the optimization procedure. Furthermore, the GP model encodes the observation uncertainties of noise-corrupted objectives, which enables an adaptive control over yield estimations. By ensuring high estimation accuracies for promising designs while tolerating higher variabilities for low-yield ones, the proposed method can significantly cut down the average computational cost of yield estimations without surrendering the accuracy of the final result. Experimental results show that, compared with the state-of-the-art yield optimization approaches, the proposed method can significantly reduce the number of circuit simulations without compromising optimization efficacy.
At present, increasing the torque density is one of the main directions in the design of special motors. The application of soft magnetic materials with high saturation magnetic flux density can ...further improve the torque performance of the motor. The continuous casting slab (CCS) explored in this manuscript belongs to silicon steel (SS), which is an alloy sample extracted from the slab before the rolling of SS. CCS has the characteristics of high saturated magnetic flux density, although its iron loss characteristics are similar to the DT4C, but it avoids the expensive cost of SS processing. In summary, its magnetic and mechanical characteristic are tested to explore the torque impact of its application in the design of high torque density motors, aiming to provide design references for the development and application of new materials for iron cores.
An RF integrated circuit design heavily relies upon experienced experts to iteratively tune the circuit parameters. A Bayesian optimization (BO) method is explored in existing works for automated ...analog and RF circuit synthesis. The overall performance can be further improved by constructing a model to exploit the correlation among different circuit specifications. In this article, we propose a BO approach for RF circuit synthesis via a multitask neural network enhanced Gaussian process (MTNN-GP). We present a novel multioutput GP model, in which the kernel functions of multiple outputs are constructed from a multitask neural network with shared hidden layers and task-specific layers. Therefore, the correlation between the outputs can be captured by the shared hidden layers. Our proposed MTNN-GP-based BO method is compared with several state-of-the-art BO methods on three real word RF circuits and achieves best performance. The experimental results demonstrate the effectiveness and efficiency of our proposed method.
Upgrading furfuralcohols and furfurals to furancarboxylic acids is of great significance for high value‐added downstream chemicals synthesis and biomass conversion. Developing an efficient catalyst ...is the key to acquiring a completely sustainable process. Herein, nitrogen‐doped carbon‐supported bimetallic AuPd bowl‐like catalysts were synthesized. The surface wettability of nitrogen‐doped carbon was well adjusted by the nitrification process. Benefiting from the alloying effect of bimetallic AuPd catalyst and the formation of hydroxyl radical initiated by H2O dissociation on the hydrophilic surface of nitrated nitrogen‐doped carbon, base‐free aerobic oxidation of 5‐hydroxymethylfurfural (HMF) could produce the highest 2,5‐furandicarboxylic acid (FDCA) yield of 93.9 %. In‐situ infrared spectroscopy uncovered adsorption configuration of HMF, and the nitrated carbon surface was favorable for HMF and intermediates to enter the active sites, greatly promoting the catalytic oxidation process. Employing other furfuralcohols (furfuryl alcohol, furan‐2,5‐diyldimethanol, 2,5‐bishydroxymethylfuran) as well as furfural and 5‐methylfurfural as starting materials, 35.6–95.4 % yield of furancarboxylic acids (FDCA, 2‐furoic acid, 5‐methyl‐2‐furoic acid) were also obtained. Moreover, the developed catalysts could maintain excellent stability and activity after four successive runs. This deep insight into the role of bimetallic synergy and surface wettability provides a basis for the rational design of the highly efficient catalysts for the oxidation of furfuralcohols and furfurals and related reactions.
Take a bow(l): Benefiting from the alloying effect for supported bimetallic AuPd catalyst and the formation of hydroxyl radical initiated by H2O dissociation on hydrophilic surface, base‐free aerobic oxidation of furfuralcohols and furfurals to furancarboxylic acids is performed over AuPd/pBNC‐x%HNO3 bowl‐like catalysts.
Nitrogen-doped carbon materials have attracted enormous interest in catalysis owing to their outstanding catalytic performance. In this work, nitrogen-doped carbonaceous catalysts (NCC) supported on ...inexpensive and naturally abundant halloysite nanotubes were successfully synthesized via precipitation polymerization, calcination, and sulfonation processes. The physical and chemical properties of the obtained catalysts were systematically characterized by different methods. The results indicated that NCC catalysts had mesoporous structures, excellent thermostability and acid-base bi-functional active sites. One-pot synthesis of 5-hydroxymethylfurfural (HMF) from glucose was performed to investigate the synthesized NCC catalysts. Benefiting from the synergistic effects of the acid-base bi-functional active sites, the highest HMF yield (62.8%) was achieved in an isopropanol-mediated DMSO system under optimal conditions. Moderate to excellent yields of HMF were also obtained from one-pot conversions of other carbohydrates, including inulin, sucrose, cellobiose, maltose and starch, with our developed catalytic system. The one-pot production of HMF from cellulose was also smoothly processed by the NCC bi-functional catalyst in an IL-based system. This work has developed a versatile strategy for designing nitrogen-doped carbonaceous catalysts that can be employed for the direct transformation of renewable carbohydrates to platform chemicals.
While the VLSI community cares about designs with high yields under process variations, expensive computational costs make conventional yield optimization methods for analog circuits inefficient for ...industrial applications. In this article, an efficient yield optimization method via the freeze-thaw Bayesian optimization technique is proposed for analog circuits. The yield analysis is integrated into the exploration process of the Bayesian optimization. With a specified Gaussian process regression method, the flexible freeze-thaw Bayesian optimization technique is utilized to automatically guide the search in the design space and control the accuracy of yield analysis in the process space. A performance optimization problem is formulated and solved to mine prior knowledge, and a further speed up is achieved. Experimental results show that the proposed method can gain a <inline-formula> <tex-math notation="LaTeX">2.47\times </tex-math></inline-formula>-<inline-formula> <tex-math notation="LaTeX">5.73\times </tex-math></inline-formula> speedup compared with the state-of-the-art methods, without loss of accuracy.
Device sizing is a challenging problem for analog circuit design. Traditional methods depend on domain knowledge and intensive simulations to search for feasible parameters. Recent studies apply the ...Bayesian optimization (BO) and a Gaussian process (GP) model in analog circuit synthesis to improve efficiency. The BO framework automatically selects the parameter candidates by inferring the surrogate GP model. However, naive BO employs a sequential updating strategy which is inefficient in a multicore environment. Besides, the widely used GP model requires costly high fidelity data, which are obtained from fine simulations. In this article, we propose a constrained batch BO approach with a multifidelity (MF) model to solve the above difficulties. The batch BO exploits parallel computing and selects promising parameters by multiple acquisition function ensemble. In addition, the MF GP model adapts the low fidelity data obtained from coarse simulations. Specifically, the proposed method incorporates information gain in a weighted clustering algorithm to refine the parameter candidates. As a result, the proposed method maintains the candidates' quality and diversity, which speeds up the optimization convergence. In the experiments, we demonstrate the efficiency of the proposed approach on three real-world circuits. The results show that our approach reduces the simulation costs by at least 54.6% compared to the state-of-the-art baselines.
In this paper, we propose an analog circuit building block generator, which is composed of a layout-aware analog circuit sizing scheme and an automated analog circuit layout generator. We reformulate ...the analog circuit sizing problem as a novel constrained multi-objective optimization problem and propose a multi-objective Bayesian optimization scheme that can find multiple different qualified designs. We further leverage a nested multi-fidelity Bayesian optimization method in layout-aware sizing to counterbalance the schematic-level simulation and the expensive post-layout simulation without losing efficiency. The automated layout generator enables the in-loop layout generation, and thus it is possible to find a set of valid post-layout results directly. The experimental results on three real-world analog circuits have demonstrated the efficiency of our proposed approach.
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