Advanced Chemical-mechanical polishing (CMP) process not only needs to maintain stable run-to-run thickness control to achieve better within wafer/within chip planarization performance, but also have ...capability to cover various topologies and layout densities patterned wafer and preventing the hot spots occurrences. In this study, different Neural-Network algorithm with data pre-processing models are implemented to the in-line CMP CLC tuning and dishing/erosion prediction at various topology/pattern density incoming pattern wafers to resolve the most challenging process issues at next generation.
A novel three-dimensional (3D) NAND structure containing both vertical gate (VG) framework and gate-all-around (GAA) cell structure is innovated and demonstrated. It is fabricated on alternating ...layers of silicon dioxide (OX) and polysilicon (PL) by using 43nm technology. To our knowledge, one of the major advantages of the novel structure is the smaller cell unit footprint than vertical channel (VC) designs; it also provides storage density comparable with VC by the use of much less cell stacks. Furthermore, GAA cell structure is expected to contain better program/erase characteristics than VG due to curvature effect. In this paper, we discuss some of the most critical processes for fabrication of such 3D NAND flash with VG-GAA designs.
This paper describes a simple and systematic etching approach for the preparation of smooth vertical bit line (BL), stacked with multiple layers of SiO 2 (OX) and poly-Si (PL) films for the use in ...three-dimensional vertical gate (3DVG) NAND flash application. A successful shape evolution from tapered to acceptable BL profile with sub-10 nm critical dimension (CD) difference between bottom and top PL layers is performed by a recipe consisting of etch-trim-etch processing steps. This novel etch sequence is more advantageous than that of traditional simultaneous etch-deposition process for controlling profile shape of the multi-layer stack in the 3D NAND flash manufacturing.
This paper applied a grain-refinement technique to develop an alternative poly-silicon floating gate. Micro-grain poly-silicon grains were refined by using a single-wafer LPCVD processor and adding ...hydrogen. The SIMS analysis of micro-grain poly-silicon films revealed that hydrogen contributed to poly-silicon formation but was not incorporated into the poly-silicon films. The grain size and dopant concentration of poly-silicon affected oxide integrity. The grain size of micro-grain poly-silicon was well controlled under 15 nm by annealing with 950°C /30s N 2 . A 100 k-cycle erase-program endurance test of a single-wafer LPCVD processor confirmed that the micro-grain floating gate poly-silicon with hydrogen had better endurance compared to conventional furnace poly-silicon.
NF 3 /NH 3 remote plasmas are used in oxide etch back process prior to the salicide process of word lines (WL) owing to high etch selectivity of silicon oxide over polysilicon. The etch saturation ...behavior which performs etch stop with a certain period of process time is one of the interesting characteristics during oxide etch process by employing NF 3 /NH 3 remote plasmas. In this study, it is found that the etch saturation behavior is correlated to wafer topology: on patterned wafer, the etch behavior at open area is similar to that on blanket oxide wafer, which shows no more oxide loss as the process reaches etch saturation. However, the phenomenon of dense area shows non-linear saturation behavior and reversely converts from silicate byproduct into silicon oxide when the process time goes over the time beyond the saturation point. Based on the concepts of thermodynamics and mass transport, we propose a possible mechanism to illustrate such a particular phenomenon.
This paper presents a case study on a process excursion where a subtle defect spray with twelve pairs of defects aggregated flow pattern on the front side of the wafer. The defect of interest is ...molten tungsten (W) balls which are generated in a dielectric etch chamber caused by plasma arcing between one part of the etch chamber and the dissimilar W film remaining on the wafer bevel. Observations of defect scans and date review collection show that the molten W balls never distribute randomly far from the arc crater in dielectric etching, but spray out over the surface of the wafer in subsequent oxygen ash processing. A possible formation mechanism for the defect spray is proposed. The two primary assumptions involved in the formation of such spray are non-uniform conductive oxygen fluid flowing over the surface of the wafer, and charged molten W balls being moved on the surface of the wafer. To eliminate the defect spray, several promising solutions are identified. This case study confirms that high conductivity p/p + -type Si substrate or the use of a different model of ash chamber with more uniform optimal gas flow distribution will improve yield.
Despite vertical stacking, the lateral scaling of 3D NAND Flash is critically important because otherwise >;16 stacking layers are needed to be cost competitive to 20nm 2D NAND. In this work, we ...propose a 3D vertical gate (VG) NAND using a self-aligned independently controlled double gate (IDG) string select transistor (SSL) decoding method. The IDG SSL provides excellent program inhibit and read selection without any penalty of cell size increase, making our 3D VG NAND cell as scalable as conventional 2D NAND. We present the world's first <; 50nm (37.5nm) half-pitch 3D NAND. The BL decoding and page operation methods are illustrated in detail. This highly pitch scalable VG with IDG SSL approach provides a very cost competitive 3D NAND.
Severe and unexpected yield loss (~26% in avg.) is found in the early development stage of the advanced flash memory. The major failure mode, array bridging contact, is revealed as the root cause and ...mainly induced by undercutting photo-resist (PR) profile. In this work, a novel scheme, anti-etch bottom anti-reflective coating (anti-etch BARC), is used instead of the conventional dual ARC (BARC/dielectric ARC, DARC) stacks on amorphous carbon layer (ACL) for contact hole patterning. Herein, we successfully demonstrate to eliminate the failure issue, greatly improve the yield and provide a promising solution with manufacturing feasibility.
•3D NAND from CNA to CUA suffers Short Channel Effect on P-type MOS since the thermal budget of array would be fully executed on CMOS transistor.•A systematic study of the cold carbon implantation on ...p-type MOS of 3D NAND with CUA is performed.•Application of cold carbon implantation on 96 layer 3D NAND with CUA improves MOS characteristics when decreasing the gate length and distance of poly to contact.
Continuous scaling the 3D NAND technology from CMOS Near Array (CNA) to CMOS Under Array (CUA) can achieve a minimal cell footprint and die size. However, the CMOS performance needs to overcome the short channel effect (SCE) and dopant deactivation since the thermal budget of the array cell would be fully executed on the CMOS transistor when 3D NAND architecture changes from CNA to CUA. Applying Cryogenic technology and carbon co-implantation can boost the CMOS performance by reducing implant induced defects in end of range (EOR) and controlling the interstitials to minimize dopants, such as boron or phosphorus, transient enhanced diffusion (TED) during subsequent thermal process. In this paper, using cold carbon implantation on P-type MOS S/D extension and P-type plug contact process of 96 layer 3D NAND FLASH memory with CUA structure can improve the device characteristics when decreasing the gate length and distance of the poly to contact, such as less SCE and better device On/Off performance. Besides, junction variability improvement is also demonstrated.
Down-flow plasma etching is mentioned instead of high-density capacitively coupled plasma (CCP) etching to prevent the control gate (CG) against physical damage during the intra-level dielectric ...(ILD) etch back, which is the process prior to form cobalt silicide word lines. However, owning to lack of ion bombardment, it is hard to achieve good etch uniformity. This paper presents the design of experiments (DOE) in varied the parameters of RF power and the chemistry ratio of NH 3 /NF 3 to achieve the optimal condition on the etch uniformity improvement. As a result, the cobalt silicide gate Rs distribution is improved ca. 150% at dense region and ca. 40% at periphery region, respectively.
