During silicon oxide hard-mask-based Al metal line patterning, the imperceptible CFx polymer featured with solvent-like residues around wafer backside bevel area was detected by energy dispersive ...x-ray spectroscopy (EDS) after conventional cleaning scheme (O2 ashing plus wet cleaning). In this study, additional bevel etching process and wafer pin-up function applied in O2 plasma asher before wet cleaning both could completely remove such solvent-like residues from wafer backside bevel area.
Advanced Chemical-mechanical polishing (CMP) process not only needs to maintain stable run-to-run thickness control but also achieve better within wafer/within chip planarization performance. ...Furthermore, slurries or other consumable parts, like PAD and Disks selection are also the keys for CMP process optimization. The most difficult thing in CMP process is to have capability to predict and cover the various topologies and layout densities patterned wafers and preventing the hot spots occurrences. In this study, different Neural-Network algorithm with data pre-processing models are implemented to the in-line CMP CLC tuning and dishing/erosion prediction at various topology/pattern density test vehicle pattern wafers. Transfer learning technique is implemented on the original Neural -Network algorithm model, the behavior of real product can be simulated and predicted based on the knowledge of test vehicle database successfully. With the aid of multiple layer erosion/ dishing Neural-Network algorithm model prediction, the potential high risky hot spots can be highlighted at the initial layout design stage, then further shorten the turn-around time of design layout validation.
Defect classifications are the very important steps as the in-line defect inspection of the semiconductor manufacturing procedure. The conventional defect classifications are usually through visual ...judgement by engineer or technical assistant. However, it's time-consuming and laborious. In our recent study, the artificial intelligence automatic defect classification (AI-ADC) performed promisingly good accuracy and purity (A/P) of the auto defect classification by deep learning method. Nevertheless, some kinds of tiny defects are not only suffered lower A/P issues, but also suffered bad A/P stability of real defect classification. In this work, we propose the novel method, called "Hierarchical structure AI-ADC", which introduced a second binning classifier and it's based on hierarchical clustering to achieve more precise defect classification. As a result, the proposed method shown obvious improvements to the binning purity of multi-lines bridge defect from 56% to 88% as well as the stability variation has been reduced from 55% to 22%, besides it also can be applied to classify the similar defect types efficiently. Indeed this approach achieves excellent defect classification and highly stable performance.
In the latest 3D NAND product development, top via hole etch process is almost the last hole connecting process to complete a device fabrication. However, we encountered severe film damaged defects ...leading to a loss of over 30% in yield. Through a series of analyses, we uncovered the underlying root cause that relates to the presence of extensive metal defects embedded beneath the layer of inter-metal dielectric (IMD). As via hole etching down through IMD, unexpectedly arcing was happened because of overcharging onto these floating metal defects in plasma. This phenomenon has had a detrimental impact on process stability and yield. This paper comprehensively reports the mechanisms of defect formation and film breakdown damage on the structure. We also propose a solution to mitigate the problem and recover the yield effectively.
•N-rich silicon nitride film with a wide range N/Si ratio by PEALD process.•Study the kinetics of the PEALD process for N-rich silicon nitride films.•The application of N-rich silicon nitride films ...as charge-trapping layer in MAONOS devices.
An N-rich silicon nitride film, with a lower refractive index (RI) than the stoichiometric silicon nitride (RI=2.01), was deposited by alternating the exposure of dichlorosilane (DCS, SiH2Cl2) and that of ammonia (NH3) in a plasma-enhanced atomic layer deposition (PEALD) process. In this process, the plasma ammonia was easily decomposed to reactive radicals by RF power activating so that the N-rich silicon nitride was easily formed by excited ammonia radicals. The growth kinetics of N-rich silicon nitride were examined at various deposition temperatures ranging from 400°C to 630°C; the activation energy (Ea) decreased as the deposition temperature decreased below 550°C. N-rich silicon nitride film with a wide range of values of refractive index (RI) (RI=1.86–2.00) was obtained by regulating the deposition temperature. At the optimal deposition temperature, the effects of RF power, NH3 flow rate and NH3 flow time were on the characteristics of the N-rich silicon nitride film were evaluated. The results thus reveal that the properties of the N-rich silicon nitride film that was formed by under plasma-enhanced atomic layer deposition (PEALD) are dominated by deposition temperature. In charge trap flash (CTF) study, an N-rich silicon nitride film was applied to MAONOS device as a charge-trapping layer. The films exhibit excellent electron trapping ability and favor a fresh cell data retention performance as the deposition temperature decreased.
The TiN was conventionally used as barrier layers for both tungsten plug and AlCu metal lines. This paper reveals a novel back end of line (BEOL) self-aligned double patterning (SADP) technology, ...which applied TiN as a spacer material. The relative processes are introduced and discussed in detail. The new SADP approach was further applied for Cu damascene structure constructions in the advanced non-volatile memory (NVM).
A collection of slides from the authors' conference presentation about the blind contact detection in the irregularly periphery area using leap and scan e-beam inspection is presented.
The authors investigated the correlation between variation of post-etch critical dimension (ECD) and etcher chamber condition during floating gate etching process. This paper presents the ...significantly effective method of utilizing the SF 6 /O 2 -based very long plasma-chamber cleaning or the novel Transformer coupled plasma (TCP) window temperature design not only achieves a stable gate CD (CD variation <; 2nm) but also simplifies etching process.
Presents a collection of slides covering the following topics: inspection; review inspector cycle optimization methodology; PL3 HardMask etch nuisance rate reduction; STI etch nuisance rate reduction ...and process development.
A collection of slides from the author's conference presentation about the metal grain suppression and DOI capture rate improvement in 32 nm technology node is presented.
