A failure electrical case caused from high leakage current between common source lines (CSL) and word-lines (WL) in 3D NAND is reported in this paper. Physical failure analyses (PFA) of leakage path ...revealed direct physical shorting between deep slit trench (SLT) and vertical channels (VC), and the hot spot delayer from its surface to the bottom by plasma focused ion beam (PFIB) exposed more and more abnormal notching profiles along SLT sidewalls toward VC. It is suspected that charges existing in the VC affecting the plasma trajectory could be the cause. The abnormal profiles can be successfully eliminated through optimizing etch recipe and optioning specific hardware configuration of the etching chamber. As a result, the failure item attributed to WL leakage is suppressed with >95% of pass ratio for device operation.
This paper presents a unique gate structure for reducing shorts between word lines on charge-trapping flash cell memory. In the early stage of developing sub-45 nm half-pitch word line by a ...self-aligned double patterning (SADP) technology, the cell array suffered from abnormal intrinsic word line-to-word line shorts, ca. 96.3% of the bridge rate on the 72 Mb cell memory, due to the formation of polysilicon residues called stringers. The increase of polysilicon over-etching to eliminate stringers involves a trade-off between the removal efficiency of stringers and the feature size maintenance. Hence, a novel bottle-shaped gate profile was tailor-made and studied. As a result, the bridge rates are dramatically suppressed to 0%~10% on the low-density flash cells and ca. 22% in average on the high-density 512 Mb flash cell memory. The novel bottle-shaped gate structure is successfully implemented in advanced charge-trapping flash memory development.
In NAND flash, devices are normally erased to negative Vt and then programmed to positive Vt. In this work we introduce a novel depletion-mode (normally on) buried-channel, junction-free n-channel ...NAND flash device. The buried-channel NAND flash shifts the P/E Vt ranges below those for the conventional surface-channel device, and is more suitable for the NAND Flash memory design. Due to the lower initial Vt, the device shows faster erase speed and higher immunity to read disturb. Furthermore, the buried-channel device has significantly improved cycling endurance, because the buried channel is insensitive to the interface state (Dit) generation during program/erase stressing. A lightly doped shallow n-type channel serves both as the buried bit line and as the source/drain of the junction-free structure. The short channel effects are overcome by using FinFET. The buried-channel NAND flash uses a simple program-inhibit method by directly raising the buried bit line potential without introducing a deep depletion in the conventional self-boosting method. A successful sub-30 nm buried-channel FinFET BE-SONOS NAND flash with MLC is demonstrated.
We have developed a new Self-aligned poly (SAP) process to improve the tunnel oxide integrity by optimizing the shallow trench isolation (STI) corner rounding profile and reducing the local oxide ...thinning effect. It is found that double in-situ steam generation (ISSG) liner oxides can effectively improve the STI corner rounding. As for the local oxide thinning effect, the composite pad dielectrics (C-Pad) composed of SiO 2 /poly-Si are good to prevent local thinning of tunnel oxide at STI corner. Moreover, using ISSG tunnel oxide can further reduce the local oxide thinning effect. Excellent breakdown characteristics of tunnel oxide by optimizing the key technologies have been verified in this work.
The 3D NAND architecture stacked with 2-deck vertical channels array structures above CMOS device was fabricated. With developing the integrated structure, a specific post-etch defect type was easily ...observed in some kinds of high aspect ratio etching processes. The defect adder poses a substantial yield risk due to its subtle physical characteristics with array underlying films punched. Upon the reviewing of overall defect classified bins, the defect adder is related to the film bump defect, which would induce organic resist incompletely covered on the bumped topography and form de-focused spot during lithography. Where the resist de-focused spot located would be generated the damage pits in etching, especially, during high aspect ratio etching process to produce seriously broken underlying films. The identifications and the suppression treatments from the resources of such defect of interest are presented.
Defect classifications are the very important steps as the in-line defect inspection of the semiconductor manufacturing procedure. The precisely identify the defect morphology based on scanning ...electron microscopy (SEM) images can provide crucial information to find out the root causes of those defects. The conventional defect inspection steps are usually through visual judgement by engineer or technical assistant. However, it's time-consuming and laborious. In our recent study, the Artificial Intelligence Automatic Defect Classification (AI-ADC) performs promising good accuracy and purity of the auto defect classification by deep learning method. Nevertheless, some kind of tiny defects are still difficult to classify by this method, such as multi-lines bridge defect. In this paper, we propose the novel method, called "Hi-erarchical structure AI-ADC", which join a second binning classifier for more precise defect classification. As a result, the proposed hierarchical AI-ADC method not only can improve the multi-lines bridge defect binning purity from 56% to 88%, but also be applied to classify the similar defect types. Indeed this approach achieves high defect classification performance.
The present study investigates the charge trapping characteristics of Si-rich nitride thin films in detail by using the gate-sensing and channel-sensing (GSCS) method. Analytical results indicate ...that thicker (>7 nm) nitride thin films are fully-capturing; the trapped electrons are distributed in the center of the nitride, and the charge centroid is independent of the N/Si ratio. However, thinner nitride layers have significantly lower capture efficiency. Using silicon-rich nitride can improve capture efficiency and make the nitride thickness more scalable. Si-rich nitride can enhance the electron de-trapping speed under -FN erase, while at the expense of worse data retention. These results indicate that Si-rich nitride introduce more dangling bonds that increase more trap sites as well as more shallower traps.
For silicon selective epitaxy growth (Si-SEG) process, an ex situ pre-epitaxial treatment (PET) is applied in order to remove the damaged layer and impurities. In this work, we observe asymmetric Si ...recess formed at the bottom of vertical channel (VC) holes in varied staircase environments leading to non-uniform, poor Si-SEG quality. A proposed symmetric silicon oxide/nitride (ON) film stack environment around VC holes by a given REG shift or via applicable layout modification manages to provide balanced charging potential to form symmetric Si etched recess inside VC holes post PET process. Subsequently, the Si-SEG process can form uniform epitaxial Si height at the bottom of VC in 3D NAND fabrication.
The challenges of oval-shaped silicon dioxide and polysilicon (OP)-layer hole etching, including shape deformation, local arcing, and adjacent hole bridging are reported. We explore the shape ...deformation evolution step by step and point out that wiggling of the organic mask is the most critical factor to enhance the occurrence of shape deformation. Further, the local arcing induced profile damage during hole-patterned etching could be eliminated by stacking specific capping materials on the top of OP layers. A DOE of the etch process demonstrates the ability to solve the adjacent hole bridging issue.
The reliability properties of BE-SONOS (Lue et al., 2005) are extensively studied. BE-SONOS employs a multi-layer O1/N1/O2/N2/O3 stack, where O1/N1/O2 serves as a bandgap engineered tunneling barrier ...that provides an efficient hole tunneling erase but eliminates the direct tunneling leakage. BE-SONOS can overcome the fundamental limitation of the conventional SONOS, for which fast erase speed and good data retention cannot be simultaneously achieved. This work provides a comprehensive understanding of the reliability of BE-SONOS. Various processes to form the critical O1/N1/O2 barrier, the trapping layer (N2), and the top blocking oxide (O3) are investigated. The results of this work provide design and processing guidelines for optimizing the performance and reliability of BE-SONOS flash memory devices.
