We propose a fully-integrated temperature sensor for battery-operated, ultra-low power microsystems. Sensor operation is based on temperature independent/dependent current sources that are used with ...oscillators and counters to generate a digital temperature code. A conventional approach to generate these currents is to drop a temperature sensitive voltage across a resistor. Since a large resistance is required to achieve nWs of power consumption with typical voltage levels (100 s of mV to 1 V), we introduce a new sensing element that outputs only 75 mV to save both power and area. The sensor is implemented in 0.18 μm CMOS and occupies 0.09 mm 2 while consuming 71 nW. After 2-point calibration, an inaccuracy of + 1.5°C/-1.4°C is achieved across 0 °C to 100 °C. With a conversion time of 30 ms, 0.3 °C (rms) resolution is achieved. The sensor does not require any external references and consumes 2.2 nJ per conversion. The sensor is integrated into a wireless sensor node to demonstrate its operation at a system level.
This paper presents a fully integrated energy harvester that maintains >35% end-to-end efficiency when harvesting from a 0.84 mm 2 solar cell in low light condition of 260 lux, converting 7 nW input ...power from 250 mV to 4 V. Newly proposed self-oscillating switched-capacitor (SC) DC-DC voltage doublers are cascaded to form a complete harvester, with configurable overall conversion ratio from 9× to 23×. In each voltage doubler, the oscillator is completely internalized within the SC network, eliminating clock generation and level shifting power overheads. A single doubler has >70% measured efficiency across 1 nA to 0.35 mA output current ( >10 5 range) with low idle power consumption of 170 pW. In the harvester, each doubler has independent frequency modulation to maintain its optimum conversion efficiency, enabling optimization of harvester overall conversion efficiency. A leakage-based delay element provides energy-efficient frequency control over a wide range, enabling low idle power consumption and a wide load range with optimum conversion efficiency. The harvester delivers 5 nW-5 μW output power with >40% efficiency and has an idle power consumption 3 nW, in test chip fabricated in 0.18 μm CMOS technology.
As battery size decreases due to system size constraints in miniature Internet-of-things systems, the internal resistance of the battery increases, resulting in a large IR drop on the battery ...voltage, complicating battery supervising functions. In this paper, we discuss low-power battery voltage supervisors (BVSs) that are capable of handling this increased IR drop. Battery voltage, battery internal resistance, required threshold voltages, and power-on-reset delay are discussed. As examples, two low-power BVSs fabricated in a 180 nm CMOS process are described.
We present a discontinuous harvesting approach for switch capacitor dc-dc converters that enables ultralow-power energy harvesting. Smart sensor applications rely on ultralow-power energy harvesters ...to scavenge energy across a wide range of ambient power levels and charge the battery. Based on the key observation that energy source efficiency is higher than charge pump efficiency, we present a discontinuous harvesting technique that decouples the two efficiencies for a better tradeoff. By slowly accumulating charge on an input capacitor and then transferring it to a battery in burst mode, dc-dc converter switching and leakage losses can be optimally traded off with the loss incurred by nonideal maximum power point tracking operation. Harvester duty cycle is automatically modulated instead of charge pump operating frequency to match with the energy source input power level. The harvester uses a hybrid structure called a moving-sum charge pump for low startup energy upon a mode switch, an automatic conversion ratio modulator based on conduction loss optimization for fast conversion ratio increment, and a <;15-pW asynchronous mode controller for ultralow-power operation. In 180-nm CMOS, the harvester achieves >40% end-to-end efficiency from 113 pW to 1.5 μW with 20-pW minimum harvestable input power.
A syringe-implantable electrocardiography (ECG) monitoring system is proposed. The noise optimization and circuit techniques in the analog front-end (AFE) enable 31 nA current consumption while a ...minimum energy computation approach in the digital back-end reduces digital energy consumption by 40%. The proposed SoC is fabricated in 65 nm CMOS and consumes 64 nW while successfully detecting atrial fibrillation arrhythmia and storing the irregular waveform in memory in experiments using an ECG simulator, a live sheep, and an isolated sheep heart.
A novel harvesting interface for multiple piezoelectric transducers (PZTs) is proposed for high-voltage energy harvesting. Pre-biasing a PZT prior to its mechanical deformation increases its damping ...force, resulting in higher energy extraction. Unlike the conventional harvesters where a PZT-generated output is assumed to be continuous sinusoidal and output polarity is assumed to be alternating every cycle, PZT-generated output from human motion is expected to be random. Therefore, in the proposed approach, energy is invested to the PZT only when PZT deformation is detected. Upon the motion detection, energy stored at a storage capacitor (
) from earlier energy harvesting cycle is invested to pre-bias PZT, enhancing energy extraction. The harvested energy is transferred to back
for energy investment on the next cycle and then excess energy is transferred to the battery. In addition, partial electric charge extraction (PECE) is adapted to extract a partial amount of charges from the PZT every time its voltage approaches the process limit of 40 V. Simulations with 0.35 µm BCD process show 7.61× (with PECE only) and 8.38× (with PECE and energy investment) improvement compared to the conventional rectifier-based harvesting scheme Proposed harvesting interface successfully harvests energy from excitations with open-circuit voltages up to 100 V.
A dual-slope capacitance-to-digital converter for pressure-sensing is presented and demonstrated in a complete microsystem. The design uses base capacitance subtraction with a configurable capacitor ...bank to narrow down input capacitance range and reduce conversion time. An energy-efficient iterative charge subtraction method is proposed, employing a current mirror that leverages the 3.6 V battery supply available in the system. We also propose dual-precision comparators to reduce comparator power while maintaining high accuracy during slope conversion, further improving energy efficiency. The converter occupies 0.105 mm 2 in 180 nm CMOS and achieves 44.2 dB SNR at 6.4 ms conversion time and 110 nW of power, corresponding to 5.3 pJ/conv-step FoM. The converter is integrated with a pressure transducer, battery, processor, power management unit, and radio to form a complete 1.4 mm × 2.8 mm × 1.6 mm pressure sensor system aimed at implantable devices. The multi-layer system is implemented in 180 nm CMOS. The system was tested for resolution in a pressure chamber with an external 3.6 V supply and serial communication bus, and the measured resolution of 0.77 mmHg was recorded. We also demonstrated the wireless readout of the pressure data on the stack system operating completely wirelessly using an integrated battery.
A Dual-Edge-Triggered (DET) flip-flop (FF) that can reliably operate at low voltage is proposed in this paper. Unlike the conventional Single-Edge-Triggered (SET) flip-flops, DET-FFs can improve ...energy efficiency by latching input data at both clock edges. When combined with aggressive voltage scaling, significant efficiency improvement is expected. However, prior DET-FF designs were susceptible to Process, Voltage and Temperature (PVT) variations, limiting their operation at low voltage regimes. A fully static true-single-phase-clocked DET-FF is proposed to achieve reliable operation at voltages as low as a near-threshold regime. Instead of the two-phase or pulsed clocking scheme in conventional DET-FFs, a True-Single-Phase-Clocking (TSPC) scheme is adopted to overcome clock overlap issues and enable low-power operation. Fully static implementation also enables robust operation in a low voltage regime. The proposed DET-FF is designed in 28nm CMOS technology, and a comprehensive analysis including post-layout Monte Carlo simulation for wide PVT ranges is performed to validate the design approaches. Extensive analysis and comparison with prior-art DET-FFs confirmed that the proposed DET-FF can operate at the lowest voltage of 0.28 V for a temperature range of -40 °C to 120 °C while maintaining nearly-best energy efficiency and power-delay-product.
Accurate measurement of synchronization cycle time is required for ultra-low power wireless sensor nodes with stringent power budgets. A multi-stage gate-leakage-based timer with boosted charging is ...proposed to address the high jitter of prior-art gate-leakage-based timers. The key approaches are faster load capacitor charging, wider voltage swing, and an improved gain sensing inverter. The proposed timer reduces RMS jitter by 8.1× and synchronization uncertainty by 4.1×, which allows hourly tracking with 200 ms uncertainty while consuming 660 pW. A novel closed-loop temperature compensation scheme with dynamic leakage adjustment is also proposed to achieve temperature sensitivity of 31 ppm/°C.
Multi‐valued logic (MVL) computing, which uses more than three logical states, is a promising future technology for handling huge amounts of data in the forthcoming “big data” era. The feasibility of ...MVL computing depends on the development of new concept devices/circuits beyond the complementary metal oxide semiconductor (CMOS) technology. This is because many CMOS devices are required to implement basic MVL functions, such as multilevel NOT, AND, and OR. In this study, a novel MVL device is reported with a complementarily controllable potential well, featuring the negative differential transconductance (NDT) phenomenon. This NDT device implemented on the WS2–graphene–WSe2 van der Waals heterostructure is evolved to a double‐NDT device operating on the basis of two consecutive NDT phenomena via structural engineering and parallel device configuration. This double‐NDT device is intensively analyzed via atomic force microscopy, kelvin probe force microscopy, Raman spectroscopy, and temperature‐dependent electrical measurement to gain a detailed understanding of its operating mechanism. Finally, the operation of a quaternary inverter configured with the double‐peak NDT device and a p‐channel transistor through Cadence circuit simulation is theoretically demonstrated.
The negative differential transconductance (NDT) device is implemented on the WS2–graphene–WSe2 van der Waals heterostructure. This NDT device is then expanded to the double peak NDT device by connecting two different NDT devices (type‐1 and type‐2) in parallel. A quaternary inverter configured with a double peak NDT device and a p‐channel transistor operates with four stable logic states.
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