There may exist many high-energy particles in spacecraft, so the FPGA circuits design needs corresponding sensitivity analysis and security reinforcement of anti-SEE (Single-event effects). However, ...it may be impractical to perform such measures to all modules of FGPA circuits due to limited resources. To identify the key modules which have a vital impact on the design and operation of FPGA circuits in spacecraft, this paper presents a novel scheme based on complex network for modeling the modules considering both the circuit functional structure and signal interaction relationship between modules. First, complex networks like MSN (Module Structure Network) and SFN (Signal Flow Network) are established to identify modules by treating each module as a node, and indicators including degree centrality (DC), betweenness centrality (BC), clustering coefficient (CC), etc., are calculated. Then, an entropy-weight method (EWM) is utilized to calculate the indicators comprehensively for identifying key modules. Next, network efficiency and sensitivity analysis are performed for failure modes. Finally, a case study is carried out, demonstrating the effectiveness of the proposed scheme for the key module identification. This work provides useful technical support for engineers in spacecraft FPGA circuits design and performance enhancement.
A novel concept of a true random number generator (TNRG) based on two metastable flip-flops in a FPGA circuit is introduced. Most of metastable based TRNG solutions are based on the assumption of a ...D-latch (flip-flop) state's uncertainty which is the source of randomness. In the proposed approach direct proximity of the metastable point is not necessary. Difference of the time of response of a pair of nearly metastable flip-flops lies upon the proposed circuit's principle of operation. It can be implemented in common programmable FPGA or CPLD circuits ensuring randomness quality-passing NIST, Diehard and Matlab tests.
Interconnect estimation for FPGAs Kannan, P.; Bhatia, D.
IEEE transactions on computer-aided design of integrated circuits and systems,
08/2006, Letnik:
25, Številka:
8
Journal Article
Recenzirano
Interconnect planning is becoming an important design issue for large field programmable gate array (FPGA)-based designs. One of the most important issues for planning interconnection is the ability ...to reliably predict the routing requirements of a given design. In this paper, a new methodology, called fast generic routability estimation for placed FPGA circuits (fGREP), for fast and reliable estimation of routing requirements for placed circuits on island-style FPGAs, is introduced. This method is based on newly derived detailed router characterizations that are introduced in this paper. It is observed that the router has a limited number of available routing elements to use and the number is proportional to the distance from a net's terminal. This is defined as the routing flexibility and an estimate for interconnect requirements is derived from it. This method is able to predict the distribution of interconnect requirements, with very fine granularity, across the entire device. The interconnect-distribution information is used to estimate congestion and total wirelength. Multiterminal nets are efficiently handled, without the need for net decomposition. This method is generic enough to enable its usage with any standard FPGA place-and-route design flow and for any island-style FPGA architecture. The method is also applicable to application-specific integrated circuit (ASIC) design flows. Experimental results on a large set of standard benchmark examples show that the estimates obtained here closely match with the detailed routing results of the state-of-the-art router PathFinder , as implemented in the well-known FPGA physical design suite VPR.
The paper presents a discussion of properties of object classification methods utilized in processing video streams from a camera. Methods based on feature extraction, model fitting and invariant ...determination are evaluated. Petri nets are used for modelling the processing flow. Data objects and transitions are defined which are suitable for efficient implementation in FPGA circuits. Processing characteristics and problems of the implementations are shown. An invariant based method is assessed as most suitable for application in a vehicle video detector.
With the end of Dennard scaling, FPGA power consumption has become a major concern. While FPGAs are conventionally supplied by a fixed supply voltage (Vdd), recent industrial (SmartVID) and academic ...solutions (dynamic voltage scaling) have shown significant power savings by scaling the FPGA Vdd on a chip-specific or chip-and application-specific basis. However, FPGAs have historically been designed for fixed-Vdd operation, which raises the question of whether we can design FPGA circuitry that is better suited for voltage scaling. In this work, we show that conventional LUTs are more sensitive to voltage than routing, so we design different LUT circuits that are more tolerant to voltage scaling. Compared to a conventional LUT, our fastest proposed LUT reduces the average critical path delay by 14% and 47% at nominal (0.8 V) Vdd and at reduced (0.6 V) Vdd, respectively. This significant reduction in delay comes at a cost of only 8% FPGA tile area increase. Our proposed LUT designs result in lower energy-delay and energy-delay^2 products at nominal Vdd and below.
Process automation systems are widely known to be a crucial element in processing plants. Power plants, chemical, petrochemical, oil refining, food, automotive and many other processes in industry ...are vast and complex, and said to be controlled by just a handful of major players worldwide. Computer control systems and control engineering methods are at the heart of all automatically controlled processes. Motivated by practical success of modern control engineering methods in many industrial process and consumer electronics products there has been an increasing amount of work on development of new methods based on new robust, adaptive methods, numerical optimization techniques, soft computing strategies, microcomputers, decentralized control structure and hardware embedded controllers realization. The paper presents current state and development of the currently most widely used control methods, structures, and their applications to different types of automated processes. The objective of the paper is to survey and compare performance of conventional controllers with several selected advanced controllers with regard to their advantages and drawbacks in industrial applications.
In this paper we compare two different implementation of an SEC-DED HSIAO code. This comparison is made to select which is the best method to achieve better memory, from reliability point of view. In ...this paper HSIAO code is used, because is efficient for single errors correction and double error detection that appear in cache memory hierarchy. Also, we have implemented the HSIAO code with FPGA Xilinx circuits for both implementations.
The purpose of this paper is to present a Fault-Tolerance methodology for FPGA-based designs, focusing power reduction or performance enhancement during on-field operation. The methodology is based ...on a new performance sensor which predictively detects errors in critical paths, either allowing power-supply voltage (VDD) to be reduced, or clock frequency (fclk) to be raised, driving power reduction or performance increase. The HDL sensor's functionality is defined by the designer, according to the target circuit configuration in the FPGA structure. The adaptive scheme uses an Automatic Voltage and Frequency Controller (AVFC) to modify fclk and/or VDD, while still guaranteeing safe operation. The built-in sensors identify performance deviations in pre-identified critical paths during circuit operation and along product lifetime, caused by parametric variations and/or aging. The fclk increase is made possible by reducing the pessimistic safety-margins defined by standard simulation tools to account for variability. The sensors delay margins are programmable, so an adequate delay margin can guarantee safe operation. Conversely, the same performance can be achieved with lower VDD. Simulation and experimental results with Virtex 5 and Spartan 6 FPGAs show that significant performance improvements (typically, 30%) can be achieved with this methodology.
Architecture of reprogrammable processor specified for video processing Szymanski, T.; Kielbik, R.; Napieralski, A.
Experience of Designing and Applications of CAD Systems in Microelectronics. Proceedings of the VI-th International Conference. CADSM 2001 (IEEE Cat. No.01 EX473),
2001
Conference Proceeding
In this paper a reprogrammable video processor architecture is presented. The processor is based on FPGA technology so it can be programmed to work with different algorithms prepared by the user ...(i.e. edge detection). Processing performance can be very high since each algorithm definition is hardware optimized.
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