Recently, a new family of symmetry-protected higher-order topological insulators has been proposed and was shown to host lower-dimensional boundary states. However, with the existence of the strong ...disorder in the bulk, the crystal symmetry is broken, and the associated corner states are disappeared. It is well known that the emergence of robust edge states and quantized transport can be induced by adding sufficient disorders into a topologically trivial insulator, that is the so-called topological Anderson insulator. The question is whether disorders can also cause the higher-order topological phase. This is not known so far, because interactions between disorders and the higher-order topological phases are completely different from those with the first-order topological system. Here, we demonstrate theoretically that the disorder-induced higher-order topological corner state and quantized fraction corner charge can appear in a modified Haldane model. In experiments, we construct the classical analog of such higher-order topological Anderson insulators using electric circuits and observe the disorder-induced corner state through the voltage measurement. Our work defies the conventional view that the disorder is detrimental to the higher-order topological phase, and offers a feasible platform to investigate the interaction between disorders and higher-order topological phases.
New Associate Editor Craninckx, Jan
IEEE journal of solid-state circuits,
5/2018, Letnik:
53, Številka:
5
Journal Article
Recenzirano
It is with pleasure that I can introduce Prof. Pui-In (Elvis) Mak from the University of Macau, Macao, China, as a new Associate Editor for the IEEE Journal of Solid-State Circuits. He brings in a ...wide expertise in analog circuits and in RF transceivers and building blocks.
Analog mixed-signal (AMS) verification is one of the essential tasks in the development process of modern systems-on-chip (SoC). Most parts of the AMS verification flow are already automated, except ...for stimuli generation, which has been performed manually. It is thus challenging and time-consuming. Hence, automation is a necessity. To generate stimuli, subcircuits or subblocks of a given analog circuit module should be identified/classified. However, there currently needs to be a reliable industrial tool that can automatically identify/classify analog sub-circuits (eventually in the frame of a circuit design process) or automatically classify a given analog circuit at hand. Besides verification, several other processes would profit enormously from the availability of a robust and reliable automated classification model for analog circuit modules (which may belong to different levels). This paper presents how to use a Graph Convolutional Network (GCN) model and proposes a novel data augmentation strategy to automatically classify analog circuits of a given level. Eventually, it can be upscaled or integrated within a more complex functional module (for a structure recognition of complex analog circuits), targeting the identification of subcircuits within a more complex analog circuit module. An integrated novel data augmentation technique is particularly crucial due to the harsh reality of the availability of generally only a relatively limited dataset of analog circuits' schematics (i.e., sample architectures) in practical settings. Through a comprehensive ontology, we first introduce a graph representation framework of the circuits' schematics, which consists of converting the circuit's related netlists into graphs. Then, we use a robust classifier consisting of a GCN processor to determine the label corresponding to the given input analog circuit's schematics. Furthermore, the classification performance is improved and robust by involving a novel data augmentation technique. The classification accuracy was enhanced from 48.2% to 76.6% using feature matrix augmentation, and from 72% to 92% using Dataset Augmentation by Flipping. A 100% accuracy was achieved after applying either multi-Stage augmentation or Hyperphysical Augmentation. Overall, extensive tests of the concept were developed to demonstrate high accuracy for the analog circuit's classification endeavor. This is solid support for a future up-scaling towards an automated analog circuits' structure detection, which is one of the prerequisites not only for the stimuli generation in the frame of analog mixed-signal verification but also for other critical endeavors related to the engineering of AMS circuits.
Incorporating an ideal memristor into a dynamical system is an effective way to induce extreme multistability, which is easy to be verified by simulations but difficult to be detected by analog ...circuit experiments. This brief is devoted to detecting such coexisting behaviors in analog circuits. A DC-controlled memris-tor emulator is proposed to direct the operation state of the ideal memristor. Its hysteresis loops, which are flexibly tuned by the DC control signal, are detected through circuit simulations and hardware experiments. Subsequently, the DC-controlled memris-tor emulator is incorporated into a Chuas circuit, and the ex-treme multistability therein is reproduced and experimentally measured on an analog circuit. This research holds the potential for promoting analog circuit applications of multi-stable memris-tive circuits.
Several analog and digital brain-inspired electronic systems have been recently proposed as dedicated solutions for fast simulations of spiking neural networks. While these architectures are useful ...for exploring the computational properties of large-scale models of the nervous system, the challenge of building low-power compact physical artifacts that can behave intelligently in the real world and exhibit cognitive abilities still remains open. In this paper, we propose a set of neuromorphic engineering solutions to address this challenge. In particular, we review neuromorphic circuits for emulating neural and synaptic dynamics in real time and discuss the role of biophysically realistic temporal dynamics in hardware neural processing architectures; we review the challenges of realizing spike-based plasticity mechanisms in real physical systems and present examples of analog electronic circuits that implement them;we describe the computational properties of recurrent neural networks and show how neuromorphic winner-take-all circuits can implement working-memory and decision-making mechanisms. We validate the neuromorphic approach proposed with experimental results obtained from our own circuits and systems, and argue how the circuits and networks presented in this work represent a useful set of components for efficiently and elegantly implementing neuromorphic cognition.
Abstract To maintain experimental lab course work during the COVID-19 lockdowns, we chose a hybrid approach for our electronic instrumentation course and developed thereto the Advanced Learning ...Platform for Analog Circuits and Automation (ALPACA). To further meet our goals and standards, the ALPACA platform has been updated, using a Raspberry Pi Pico with Python instead of an Arduino. Our educational materials and approach are illustrated here through the typical example of a relaxation oscillator assignment. As student’s feedback was overall positive and grades remained comparable, we continue the use of the ALPACA in the non-COVID era.
Neurons can exhibit abundant electrical activities due to physical effects of various electrophysiology environments. The electromagnetic induction flows can be triggered by changes in neuron ...membrane potential, which can be equivalent to a memristor applying on membrane potential. To imitate the electromagnetic induction effects, we propose a three-variable memristor-based Wilson neuron model. Using several kinetic analysis methods, the memristor parameter- and initial condition-related electrical activities are explored intensively. It is revealed that the memristive Wilson neuron model can display rich electrical activities, including the asymmetric coexisting electrical activities and antimonotonicity phenomenon. Finally, using off-the-shelf discrete components, an analog circuit on a hardware level is implemented to verify the numerically simulated coexisting electrical activities. Studying these rich electrical activities in neurons can build the groundwork to widen the neuron-based engineering applications.
Bayesian optimization is a promising methodology for analog circuit synthesis. However, the sequential nature of the Bayesian optimization framework significantly limits its ability to fully utilize ...real-world computational resources. In this article, we propose an efficient parallelizable Bayesian optimization algorithm via multiobjective acquisition function ensemble (MACE) to further accelerate the optimization procedure. By sampling query points from the Pareto front of the probability of improvement (PI), expected improvement (EI), and lower confidence bound (LCB), we combine the benefits of state-of-the-art acquisition functions to achieve a delicate tradeoff between exploration and exploitation for the unconstrained optimization problem. Based on this batch design, we further adjust the algorithm for the constrained optimization problem. By dividing the optimization procedure into two stages and first focusing on finding an initial feasible point, we manage to gain more information about the valid region and can better avoid sampling around the infeasible area. After achieving the first feasible point, we favor the feasible region by adopting a specially designed penalization term to the acquisition function ensemble. The experimental results quantitatively demonstrate that our proposed algorithm can reduce the overall simulation time by up to <inline-formula> <tex-math notation="LaTeX">74\times </tex-math></inline-formula> compared to differential evolution (DE) for the unconstrained optimization problem when the batch size is 15. For the constrained optimization problem, our proposed algorithm can speed up the optimization process by up to <inline-formula> <tex-math notation="LaTeX">15\times </tex-math></inline-formula> compared to the weighted EI-based Bayesian optimization (WEIBO) approach, when the batch size is 15.
Most analog circuits need a current reference generator to provide a stable biasing point for the transistors. Given the limited voltage headroom in advanced node technologies, there would be notable ...restrictions on the tolerance of the reference current deviation. Use of off-chip reference generators adds to the size of the system while the on-chip reference current generators are still partially dependent on the on-chip resistor values which is prone to technology variations. We propose an on-chip reference generator with a fully off-chip resistor which has less sensitivity to process variations. Monte-Carlo simulation results shows that the proposed has 31% more precision compared to the conventional on-chip reference generator. Measurement results in Formula Omitted CMOS shows that the chip produces a stable reference current that is defined based on an off-chip resistor. The proposed structure consumes the same current as conventional and does not add to the power consumption.
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