Analog dividers are widely used in analog systems. Analog realization of such circuits suffer from limited dynamic range and non-linearity issues, therefore, extra circuitry should be required to ...compensate these types of shortcomings. In this paper a gain controllable, analog divider is proposed based on data converters. Our circuit can be implemented both in current and voltage mode by selecting proper architectures. The resolution, power consumption and operation speed can be controlled by proper selecting of components. Another advantage of our circuit is its gain programmability. Moreover, the gain can be adjusted independently based on the relationship between input signals. Our proposed method offers two different gain control abilities, one for situation that the numerator signal is bigger than the denominator, and another gain is applied when the denominator is larger than the numerator. As a result, no extra amplifier is required for signal amplification. Moreover, the input and output signal nature can be chosen arbitrarily in this circuit, i.e. input signal may be a voltage signal while the output signal is current. Simulation results from SPICE confirm the proper operation of the circuit.
A CMOS analog multiplier with a large signal bandwidth has been proposed. The multiplier is based on a variable-gain amplifier and the gain is controlled continuously in accordance with an input ...signal. A continuous-time inverter-based flash digitizer with no need of an oversampling clock serves as an enabler for the enhanced bandwidth with robust operation. The two-quadrant and four-quadrant multipliers are presented as well as a divider with the same principle. The proposed four-quadrant multiplier was designed with <inline-formula> <tex-math notation="LaTeX">0.13~\mu \text{m} </tex-math></inline-formula> CMOS process under a 1.2V supply. Simulation results proved multiplication of 100MHz input signals with 7.0mW power at typical condition. In addition, calibration of the digitizer was applied and verified under process variation. Furthermore, the divider and a fusion of the multiplier and the divider were also designed and confirmed by simulations. Since the multiplier and the divider are suitable for low-voltage operation and require no well-defined square or exponential property of MOS transistors, a larger bandwidth or lower power is expected by implementation with finer CMOS process.
In this communication, two novel architectures of voltage mode analog divider circuit and square-root circuit using an operational transconductance amplifier (OTA) have been presented. The proposed ...divider circuit employs an OTA and two MOSFETs, while the square-root circuit requires one OTA along with one MOSFET. The proposed divider circuit can also be configured as inverse voltage function generator. The performance of the proposed circuits has been validated through Cadence Virtuoso simulations using 0.18 µm CMOS technology parameters. The total power consumption for analog divider circuit is 821 µW, while for square-root circuit, it is 442 µW with ± 0.9 V power supply. Experimental results have also been provided to validate the theory.
In this communication, a current feedback operational amplifier (CFOA) based novel architecture of voltage-mode analog multiplier/divider circuit has been proposed. The proposed circuit employs a ...single CFOA and four MOSFETs. The multiplier circuit can operate in four quadrant modes, whereas, the divider circuit can operate in two quadrant modes. The applications of the proposed multiplier circuit in amplitude modulator, squarer, and frequency doubler circuit have also been presented. To check the robustness of the proposed circuit, mismatch analysis, process corner-voltage-temperature analysis, and Monte-Carlo simulations have been performed. Noise analysis has also been carried out and the output noise for multiplier and divider circuits are found to be below 0.28 μV /sqrt(Hz). The presented circuit has been simulated with CMOS CFOA implemented using 0.18 μm TSMC technology parameters.
This paper proposes an accurate tunable‐gain 1/x circuit. The output voltage of the 1/x circuit is generated by using a capacitor charging time that is inversely proportional to the input voltage. ...The output voltage is independent of the process parameters, because the output voltage depends on the ratios of the capacitors, resistors, and current mirrors. The voltage gain of the 1/x circuit is tuned by a 10‐bit digital code. The 1/x circuit was fabricated using a 0.18 μm CMOS process. Its core area is 0.011 mm2(144μm×78μm), and it consumes 278 μW at VDD=1.8V and fCLK=1MHz. Its error is within 1.7% at VIN=0.05V to 1 V.
A high-accuracy pulse-based analog divider with 12-bit digital output is proposed in this letter. Moreover, a comparator-delay-free voltage-to-pulse generator (VPG) and a pulse divider (PDV) are ...proposed: the on-time of the VPG-generated pulses is proportional to its input voltage, and is free from comparator delay; the PDV performs the functions of a divider and an analog-to-digital converter, so the output of the proposed divider is 12-bit digital code directly. The proposed chip was fabricated using a 0.35-<inline-formula> <tex-math notation="LaTeX">{{\mu }}\text{m} </tex-math></inline-formula> 2P4M 3.3-V mixed-signal polycide process. According to the measured results, the maximal error is only 1.06% and the quiescent power is only 205 <inline-formula> <tex-math notation="LaTeX">\mu \text{W} </tex-math></inline-formula>.
Present active circuitry for the linearization of thermistor temperature-voltage characteristic has drawbacks concerning the effect of connecting lead wire resistances, self-heating effect due to ...continuous excitation current in the sensing thermistor, ambient temperature variations and temperature dependent reverse saturation current both in transistorized logarithmic amplifier and Field Effect Transistor. In order to overcome these problems, a new hardware approach for the linearization of remote thermistor has been proposed. The experimental results show the good linearity throughout the temperature range of thermistor.
In recent years, very fast dividers have been required for the real‐time application of digital signal processing, robot control, and the like. This paper proposes a high‐speed cellular array divider ...with a selection function that is based on the non‐restoring algorithm and can deal with both fixed‐point and negative operands in two's complement form. This divider uses new techniques that can generate in parallel both the quotient bit of one row and a partial remainder and CLS bit of the next row. The delay time of the proposed divider is calculated in terms of a delay of one unit such as a NAND gate. Finally, by using PARTHENON, a CAD (computer‐aided design) system for VLSI, this divider is designed and evaluated. As a result, elimination of the delay time for even rows becomes possible. Thus, the delay time can be decreased to approximately one half that of the high‐speed divider proposed by Cappa and Hamacher, which uses the most general high‐speed techniques of carry‐save and CLA.
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