This book is a comprehensive guide to new design for testability (DFT) methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality ...and yield, and speed up time-to-market and time-to-volume. Key features include up-to-date coverage of design for testability, coverage of industry practices commonly found in commercial DFT tools but not discussed in other books, and numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures. Practitioners/Researchers in VLSI design and testing; design or test engineers, as well as research institutes will benefit from this book. This book is also appropriate for undergraduate and graduate-level courses in electronic testing, digital systems testing, digital logic test and simulation, and VLSI design.
New Associate Editor Sylvester, Dennis
IEEE journal of solid-state circuits,
2/2024, Letnik:
59, Številka:
2
Journal Article
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It is with great pleasure that I welcome Prof. Priyanka Raina to the Editorial Board of the IEEE Journal of Solid-State Circuits as a new Associate Editor. Prof. Raina is an expert in architectures ...and circuits for domainspecific accelerators.
This work describes the design of a 16 point analog domain FFT using a Charge Re-use Analog Fourier Transform (CRAFT) engine. The circuit relies on charge re-use to achieve 47 dB average output SNDR ...on an instantaneous input bandwidth of 5 GHz, and consumes only 3.8 mW (12.2 pJ/conv.). The CRAFT engine is used as a wide-band, low power RF front-end channelizer for software defined radio (SDR) applications. The paper also discusses the handling of circuit non-idealities for the CRAFT design: their significance, modeling, and circuit techniques for their mitigation. These techniques enable this implementation to achieve a large dynamic range even at high speeds.
This special issue of the IEEE Transactions On Circuits and Systems- PART II: EXPRESS BRIEFS (TCAS-II) continues the successful tradition of the co-publication initiative started few years ago by the ...IEEE Circuits and Systems Society (CASS) to publish a selection of the best papers accepted for presentation at the IEEE International Symposium on Circuits and Systems (ISCAS). This year ISCAS is held in Monterey, California, United States of America, on May 21 st - May 25 th , and the process for this Special Issue was carried out as soon as the paper selection was done. As TCAS-II only publishes 5-page briefs, and hence both conference and journal versions of selected works would be largely overlapped, the papers included in this Issue will not appear in the Proceedings of the IEEE ISCAS. Also, similar to what is done by other IEEE Societies, IEEE CASS intends to shift the role of IEEE conferences towards more networking events as well as opportunities for discussions on ongoing research efforts.
Random device mismatch plays an important role in the design of accurate analog circuits. Models for the matching of MOS and bipolar devices from open literature show that matching improves with ...increasing device area. As a result, accuracy requirements impose a minimal device area and this paper explores the impact of this constraint on the performance of general analog circuits. It results in a fixed bandwidth-accuracy-power tradeoff which is set by technology constants. This tradeoff is independent of bias point for bipolar circuits whereas for MOS circuits some bias point optimizations are possible. The performance limitations imposed by matching are compared to the limits imposed by thermal noise. For MOS circuits the power constraints due to matching are several orders of magnitude higher than for thermal noise. For the bipolar case the constraints due to noise and matching are of comparable order of magnitude. The impact of technology scaling on the conclusions of this work are briefly explored.
A 45 nm microprocessor core integrates resilient error-detection and recovery circuits to mitigate the clock frequency (F CLK ) guardbands for dynamic parameter variations to improve throughput and ...energy efficiency. The core supports two distinct error-detection designs, allowing a direct comparison of the relative trade-offs. The first design embeds error-detection sequential (EDS) circuits in critical paths to detect late timing transitions. In addition to reducing the Fclk guardbands for dynamic variations, the embedded EDS design can exploit path-activation rates to operate the microprocessor faster than infrequently-activated critical paths. The second error-detection design offers a less-intrusive approach for dynamic timing-error detection by placing a tunable replica circuit (TRC) per pipeline stage to monitor worst-case delays. Although the TRCs require a delay guardband to ensure the TRC delay is always slower than critical-path delays, the TRC design captures most of the benefits from the embedded EDS design with less implementation overhead. Furthermore, while core min-delay constraints limit the potential benefits of the embedded EDS design, a salient advantage of the TRC design is the ability to detect a wider range of dynamic delay variation, as demonstrated through low supply voltage (V CC ) measurements. Both error-detection designs interface with error-recovery techniques, enabling the detection and correction of timing errors from fast-changing variations such as high-frequency V CC droops. The microprocessor core also supports two separate error-recovery techniques to guarantee correct execution even if dynamic variations persist. The first technique requires clock control to replay errant instructions at 1/2F CLK . In comparison, the second technique is a new multiple-issue instruction replay design that corrects errant instructions with a lower performance penalty and without requiring clock control. Silicon measurements demonstrate that resilient circuits enable a 41% throughput gain at equal energy or a 22% energy reduction at equal throughput, as compared to a conventional design when executing a benchmark program with a 10% V CC droop. In addition, the microprocessor includes a new adaptive clock control circuit that interfaces with the resilient circuits and a phase-locked loop (PLL) to track recovery cycles and adapt to persistent errors by dynamically changing Fclk f°Γ maximum efficiency.
In this paper, we describe the design of Neurogrid, a neuromorphic system for simulating large-scale neural models in real time. Neuromorphic systems realize the function of biological neural systems ...by emulating their structure. Designers of such systems face three major design choices: 1) whether to emulate the four neural elements-axonal arbor, synapse, dendritic tree, and soma-with dedicated or shared electronic circuits; 2) whether to implement these electronic circuits in an analog or digital manner; and 3) whether to interconnect arrays of these silicon neurons with a mesh or a tree network. The choices we made were: 1) we emulated all neural elements except the soma with shared electronic circuits; this choice maximized the number of synaptic connections; 2) we realized all electronic circuits except those for axonal arbors in an analog manner; this choice maximized energy efficiency; and 3) we interconnected neural arrays in a tree network; this choice maximized throughput. These three choices made it possible to simulate a million neurons with billions of synaptic connections in real time-for the first time-using 16 Neurocores integrated on a board that consumes three watts.
RF circuit design is now more important than ever as we find ourselves in an increasingly wireless world. Radio is the backbone of today’s wireless industry with protocols such as Bluetooth, Wi-Fi, ...WiMax, and ZigBee. Most, if not all, mobile devices have an RF component and this book tells the reader how to design and integrate that component in a very practical fashion. This book has been updated to include today's integrated circuit (IC) and system-level design issues as well as keeping its classic "wire lead" material. Design concepts and tools includes:The Basics: Wires, Resistors, Capacitors, InductorsResonant Circuits: Resonance, Insertion Loss Filter Design: High-pass, Bandpass, Band-rejectionImpedance Matching: The L Network, Smith Charts, Software Design ToolsTransistors: Materials, Y Parameters, S ParametersSmall Signal RF Amplifier: Transistor Biasing, Y Parameters, S ParametersRF Power Amplifiers: Automatic Shutdown Circuitry , Broadband Transformers, Practical Winding HintsRF Front-End: Architectures, Software-Defined Radios, ADC’s EffectsRF Design Tools: Languages, Flow, Modeling
Incoming Editorial Ha, Yajun
IEEE transactions on circuits and systems. II, Express briefs,
1/2022, Letnik:
69, Številka:
1
Journal Article
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Dear Readers, It is with my great honor and privilege to start my two-year term of duty as Editor-in-Chief (EiC) of IEEE Transactions on Circuits and Systems—Part II: Express Briefs (TCAS-II). I am ...very thankful to the IEEE Circuits and Systems Society (CASS) for giving me this opportunity. During the last two years, I have been very fortunate to work as Associate Editor-in-Chief (AEiC) of TCAS-II together with Professor José M. de la Rosa, who has set the bar very high for me! I would like to begin this first issue of TCAS-II in 2022 by expressing my most sincere and warm gratitude to Professor José M. de la Rosa for his great job, dedication, and guidance during all this time working together. I learned a lot from him!
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