This letter proposes a low‐power keyword spotting (KWS) architecture based on a modified temporal efficient neural network (TENet) and a simplified mel‐frequency cepstrum coefficient (MFCC) ...algorithm. The optimized MFCC algorithm reduces the computational load by 82% for multiplications and 66% for additions. An efficient hardware architecture and data flow for TENet have been designed, resulting in a 3.1× reduction in the operating cycle compared to similar work. The parameter count and computational load are reduced by 3.7× and 2.8×, respectively, and the accuracy reaches 95.36% for ten keywords in the Google Speech Command Dataset (GSCD). Operating at a frequency of 16 KHz for MFCC and 100 KHz for NN accelerator on a 28 nm process, the power consumption overhead is 9.1 µW.
This letter proposes a low‐power keyword spotting (KWS) architecture based on a modified Temporal Efficient Neural Network (TENet) and a simplified Mel‐Frequency Cepstrum Coefficient (MFCC) algorithm. Operating at a frequency of 16 KHz for MFCC and 100 KHz for NN accelerator on a 28nm process, the power consumption overhead is 9.1 microwatts, and the accuracy reaches 95.36% for 10 keywords in the Google Speech Command Dataset (GSCD).
We review the salient features of two advanced nodes of an 8-Nb-layer fully planarized process developed recently at MIT Lincoln Laboratory for fabricating single flux quantum (SFQ) digital circuits ...with very large-scale integration on 200-mm wafers: the SFQ4ee and SFQ5ee nodes, where "ee" denotes that the process is tuned for energy-efficient SFQ circuits. The former has eight superconducting layers with 0.5-μm minimum feature size and a 2-Ω/sq Mo layer for circuit resistors. The latter has nine superconducting layers: eight Nb wiring layers with the minimum feature size of 350 nm and a thin superconducting MoN x layer (T c ~ 7.5 K) with high kinetic inductance (about 8 pH/sq) for forming compact inductors. A nonsuperconducting (T c <; 2 K) MoN x layer with lower nitrogen content is used for 6-Ω/sq planar resistors for shunting and biasing of Josephson junctions (JJs). Another resistive layer is added to form interlayer sandwich-type resistors of milliohm range for releasing unwanted flux quanta from superconducting loops of logic cells. Both process nodes use Au/Pt/Ti contact metallization for chip packaging. The technology utilizes one layer of Nb/AlO x -Al/Nb JJs with critical current density J c of 100 μA/μm 2 and minimum diameter of 700 nm. Circuit patterns are defined by 248-nm photolithography and high-density plasma etching. All circuit layers are fully planarized using chemical mechanical planarization of SiO 2 interlayer dielectric. The following results and topics are presented and discussed: the effect of surface topography under the JJs on the their properties and repeatability, I c and J c targeting, effect of hydrogen dissolved in Nb, MoN x properties for the resistor layer and for high-kinetic-inductance layer, and technology of milliohm-range resistors.
Digital Systems Design with FPGAs and CPLDs explains how to design and develop digital electronic systems using programmable logic devices (PLDs). Totally practical in nature, the book features ...numerous (quantify when known) case study designs using a variety of Field Programmable Gate Array (FPGA) and Complex Programmable Logic Devices (CPLD), for a range of applications from control and instrumentation to semiconductor automatic test equipment.Key features include: * Case studies that provide a walk through of the design process, highlighting the trade-offs involved. * Discussion of real world issues such as choice of device, pin-out, power supply, power supply decoupling, signal integrity- for embedding FPGAs within a PCB based design.With this book engineers will be able to: * Use PLD technology to develop digital and mixed signal electronic systems * Develop PLD based designs using both schematic capture and VHDL synthesis techniques * Interface a PLD to digital and mixed-signal systems * Undertake complete design exercises from design concept through to the build and test of PLD based electronic hardwareThis book will be ideal for electronic and computer engineering students taking a practical or Lab based course on digital systems development using PLDs and for engineers in industry looking for concrete advice on developing a digital system using a FPGA or CPLD as its core. * Case studies that provide a walk through of the design process, highlighting the trade-offs involved. * Discussion of real world issues such as choice of device, pin-out, power supply, power supply decoupling, signal integrity- for embedding FPGAs within a PCB based design.
As the globalization of integrated circuits (ICs) continues to advance, the threat of hardware Trojans has emerged as a major concern in ensuring the security and reliability of analog circuits. ...While a considerable body of prior work has focused on detecting digital Trojans in digital circuits, the detection of analog Trojans in analog circuits has received significantly less attention. We present DAWN, a sensitivity analysis-based analog Trojan detection framework using neural networks to identify potential analog Trojan hotspots and prevent them from being exploited through unauthorized modifications. We incorporate circuit watermarks in these hotspots to provide an additional layer of security. With these watermarks, any malicious modification to the circuit is automatically detected with high accuracy. We target the detection of stealthy, large-delay Trojans that might be inserted either during the chip design or fabrication stages. Experimental results for analog benchmark circuits and two commonly studied analog Trojans demonstrate the effectiveness of the proposed framework.
A superconducting loop stores persistent current without any ohmic loss, making it an ideal platform for energy efficient memories. Conventional superconducting memories use an architecture based on ...Josephson junctions (JJs) and have demonstrated access times less than 10 ps and power dissipation as low as 10−19 J. However, their scalability has been slow to develop due to the challenges in reducing the dimensions of JJs and minimizing the area of the superconducting loops. In addition to the memory itself, complex readout circuits require additional JJs and inductors for coupling signals, increasing the overall area. Here, we have demonstrated a superconducting memory based solely on lithographic nanowires. The small dimensions of the nanowire ensure that the device can be fabricated in a dense area in multiple layers, while the high kinetic inductance makes the loop essentially independent of geometric inductance, allowing it to be scaled down without sacrificing performance. The memory is operated by a group of nanowire cryotrons patterned alongside the storage loop, enabling us to reduce the entire memory cell to 3 m × 7 m in our proof-of-concept device. In this work we present the operation principles of a superconducting nanowire memory (nMem) and characterize its bit error rate, speed, and power dissipation.
Data centers are critical, energy-hungry infrastructures that run large-scale Internet-based services. Energy consumption models are pivotal in designing and optimizing energy-efficient operations to ...curb excessive energy consumption in data centers. In this paper, we survey the state-of-the-art techniques used for energy consumption modeling and prediction for data centers and their components. We conduct an in-depth study of the existing literature on data center power modeling, covering more than 200 models. We organize these models in a hierarchical structure with two main branches focusing on hardware-centric and software-centric power models. Under hardware-centric approaches we start from the digital circuit level and move on to describe higher-level energy consumption models at the hardware component level, server level, data center level, and finally systems of systems level. Under the software-centric approaches we investigate power models developed for operating systems, virtual machines and software applications. This systematic approach allows us to identify multiple issues prevalent in power modeling of different levels of data center systems, including: i) few modeling efforts targeted at power consumption of the entire data center ii) many state-of-the-art power models are based on a few CPU or server metrics, and iii) the effectiveness and accuracy of these power models remain open questions. Based on these observations, we conclude the survey by describing key challenges for future research on constructing effective and accurate data center power models.
In this work, the operation of n- and p-type field-effect transistors (FETs) on the same WSe2 flake is realized,and a complementary logic inverter is demonstrated. The p-FET is fabricated by ...contacting WSe2 with a high work function metal, Pt, which facilities hole injection at the source contact. The n-FET is realized by utilizing selective surface charge transfer doping with potassium to form degenerately doped n+ contacts for electron injection. An ON/OFF current ratio of >104 is achieved for both n- and p-FETs with similar ON current densities. A dc voltage gain of >12 is measured for the complementary WSe2 inverter. This work presents an important advance toward realization of complementary logic devices based on layered chalcogenide semiconductors for electronic applications.
Computing‐in‐memory (CIM) is a promising technique for solving the ‘memory wall’ and ‘power consumption wall’ problems. However, calculations in the analog domain are limited in terms of accuracy and ...sensitivity to process, voltage, and temperature changes. In this study, the authors proposed a CIM multiply‐and‐accumulate (MAC) circuit in which the MAC result was reflected by the pulse edge and converted into the final digital output using a dual‐edge counter quantization circuit, thereby improving the accuracy of the MAC operation and reducing the difficulty of quantization. The performance of the proposed CIM circuit was evaluated using a 28‐nm process. It could achieve 4‐bit multiplication without errors, with an energy efficiency of 24.38 to 670.86 TOPS/W.
In this study, the authors proposed a computing‐in‐memory multiply‐and‐accumulate (CIM MAC) circuit that could generate pulses spontaneously. The MAC result was reflected by the pulse edge and converted into the final digital output using a quantization circuit, improving the accuracy of the MAC operation and reducing the difficulty of quantization.
Here we summarize recent progress in the development of electrolyte‐gated transistors (EGTs) for organic and printed electronics. EGTs employ a high capacitance electrolyte as the gate insulator; the ...high capacitance increases drive current, lowers operating voltages, and enables new transistor architectures. Although the use of electrolytes in electronics is an old concept going back to the early days of the silicon transistor, new printable, fast‐response polymer electrolytes are expanding the potential applications of EGTs in flexible, printed digital circuits, rollable displays, and conformal bioelectronic sensors. This report introduces the structure and operation mechanisms of EGTs and reviews key developments in electrolyte materials for use in printed electronics. The bulk of the article is devoted to electrical characterization of EGTs and emerging applications.
This Review discusses recent progress in electrolyte‐gated transistors (EGTs). EGTs employ a high‐capacitance electrolyte as the gate insulator layer, which affords low voltage operation and high drive currents. The Review covers EGT operation mechanisms, the development of new solid electrolyte materials for use in EGTs and emerging applications of these devices in printed digital circuits, flexible displays, biosensors, and fundamental transport measurements.
Approximate arithmetic circuits sacrifice computing accuracy in exchange for improvements in power, area, and speed. Many approximate binary multipliers that use 4-2 compressors have been proposed ...but most of the proposals have error performances that depend on the order in which the inputs are connected to the compressors. This complicates the design and prevents a fair comparison among different approximate multipliers. The paper proposes the input order invariant approximate 4-2 compressors, whose behavior remains consistent regardless of the order of input signals. We derive the complete set of such compressors and utilize them to synthesize 8-bit multipliers. Our analysis reveals that only a limited subset of input order invariant approximate 4-2 compressors offers an optimal balance between error and power savings. Furthermore, we demonstrate that this optimal set of 4-2 compressors can be strategically distributed within the columns of the multiplier to further enhance the trade-off between error and power efficiency. The proposed circuits, once implemented in a 14 nm FinFET standard cell technology, favorably compare against the state of the art.
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