For fast buffering of large stepwise input to an nF-range capacitive load, this article presents a 5-V rail-to-rail (RTR) input–output paralleled-amplifier (PA) in which a dynamic class-C amplifier ...(DCCA) and a linear single-stage operational transconductance amplifier (OTA) are combined in parallel. During slew time, the DCCA, which is designed to consume a near-zero static current, dominantly supplies the dynamic current up to 8.5 mA to the output. When the output gets closer to the fine-settling region, the DCCA is rapidly faded out in virtue of a dedicated near-zero dead-zone control (NDZC), and it hands over to the linear OTA. A current-redistributive RTR Formula Omitted-boosting technique is also proposed so that the OTA can have a wide gain-bandwidth product (GBW) even over the RTR input range while minimizing the quiescent current dissipation. The prototype chip was fabricated only with 0.5-Formula Omitted 5-V CMOS devices, and it occupies a die area of 0.03 Formula Omitted. The proposed amplifier consumed a static current of 3.1 Formula Omitted with a supply voltage of 5 V. The slew rates (SRs) with load capacitances (Formula Omitted) of 0.8 and 10 nF were measured to be 10.3 and 0.86 V/Formula Omitted, respectively, for a step input of Formula Omitted4.2 V, which is a state-of-the-art result compared to prior chips. The measured GBW of 10–127 kHz was achieved over 0.8–10 nF Formula Omitted with ≥ 59° phase margin (PM). The measured GBW deviation in a common-mode voltage (Formula Omitted) range of 0.3–4.7 V was within the maximum of 20%.
Abstract This paper presents a high-gain, high-drive operational amplifier based on the 0.18 μm technology. The first stage employs a current-reuse common-source common-gate structure to enhance ...gain, while the second stage utilizes a transconductance-enhanced push-pull output stage. This design achieves high-drive performance while retaining a high gain. Simulation using Cadence software demonstrates that, under a 5 V power supply voltage, the amplifier exhibits a low-frequency gain of 120 dB, with output sink and source current capabilities reaching 17.7 mA and 2.53 mA, respectively.
Abstract
In order to realize the function of an automatic target-scoring system for shock wave pressure signal positioning, it is necessary to collect multi-channel shock wave pressure signals. ...Therefore, this paper designs a sensor signal acquisition and processing system based on STM32. The system can realize the acquisition and processing of 8-channel sensor signals. The hardware module includes the operational amplifier module, the acquisition conversion module, the temperature acquisition module, and the wireless transmission module. In order to solve the positioning coordinates, the program is written based on Keil uVision5 and STM32 firmware library. The PYQT5 is called to design the host computer receiving software. Finally, the acquisition test of the designed acquisition system is carried out. The test results show that the signal reduction degree of the designed acquisition system is more than 90%. The designed signal acquisition system has the advantages of high reliability and small size. It also has a certain universality.
A novel mechatronic semiactive inerter (MSAI) by using an operational amplifier (OPA) circuit-based adjustable capacitor is proposed in this study to address the realization challenge of ...fast-responding semiactive inerters. The fast-responding ability, inertance-directly controlled capability, and sensor-less regulation characteristic are distinctive advantages of the proposed MSAI. To implement a pure controlled capacitor and a pure capacitive motor load (the internal resistance of the motor is canceled), two different types of OPA circuits are designed. Tuned inerter damper and tuned viscous mass damper, as two typical MSAI-based configurations, are established and tested. It is found that the proposed MSAI can modify the inertance quickly (in the microsecond time scale) and reliably, and good congruence between theoretical and experimental results is obtained.
Abstract
A three‐stage rail‐to‐rail bulk‐driven class AB OTA that operates with ±0.15 V supplies and a power dissipation of 90 nW is introduced. The first two stages use resistive local common mode ...feedback. The OTA uses simple phase lead compensation. It has a 36 MHz.pF/μW small signal figure of merit and a 55(V/μs) pF/μW large signal figure of merit.
Active learning, which aims to enhance modeling efficiency, precision, and cost effectiveness through selective labeling, is emerging as a promising strategy for analog circuit modeling. However, ...analog circuits are constrained by strict functional and technological limitations, resulting in scarcity of data for modeling, and additional data acquisition involves expensive and time-consuming simulations. For efficient and effective active learning for analog circuit modeling, our research analyzes data-driven initial sampling techniques which lays the foundation for the active learning process. Our experiments reveal that these initialization strategies expedite the learning process, decrease the demand for extensive simulations, and produces more accurate models. Furthermore, the results demonstrate that active learning techniques, which uniformly sample the design space, tend to benefit from distance-based initialization technique.
This brief presents a chopper-stabilized low-noise multipath operational amplifier with dual ripple rejection loops. The multipath amplifier scheme has a lower noise and a wider bandwidth than the ...conventional chopper amplifiers. The dual ripple rejection loops are proposed to effectively attenuate the offset and low-frequency noise components. The dual ripple rejection loops are implemented using a feedback low-pass filter (LPF) for AC coupling and a floating high-pass filter (HPF) for additional low-frequency rejection with a fast common mode response. The amplifier is fabricated using a 0.18-μm CMOS process with an active area of 4.92 mm 2 . The input referred noise level is 6.62 nV/√Hz, and the total current consumption is 117.2 μA with a 1.8 V power supply.
A Compact 0.3-V Class AB Bulk-Driven OTA Kulej, Tomasz; Khateb, Fabian
IEEE transactions on very large scale integration (VLSI) systems,
2020-Jan., 2020-1-00, 20200101, Letnik:
28, Številka:
1
Journal Article
Recenzirano
In this article, a new solution for an ultralow-voltage (ULV) ultralow-power (ULP) operational transconductance amplifier (OTA) is presented. Thanks to the combination of a low-voltage bulk-driven ...nontailed differential stage with the multipath Miller zero compensation technique, a simple class AB power-efficient ULV structure has been obtained, which can operate from supply voltages less than the threshold voltages of the employed MOS transistors, while offering rail-to-rail input common-mode range at the same time. The proposed OTA was fabricated using the 180-nm CMOS process from Taiwan Semiconductor Manufacturing Company (TSMC) and can operate from VDD ranging from 0.3 to 0.5 V. The 0.3-V version dissipates only 12.6 nW of power while showing a 64.7-dB voltage gain at 1-Hz, 2.96-kHz gain-bandwidth product, and a 4.15-V/ms average slew-rate at 30-pF load capacitance. The measured results agree well with simulations.
The developing optimization algorithms provide promising solutions for speeding up analog integrated circuit sizing. However, the optimization of complicated circuits whose solution regions are ...narrow remains to be a challenge. With a limited number of sampling points due to the restriction of computational resources, it is difficult for traditional algorithms to achieve satisfactory results for such circuits. To solve this problem, this article proposes a rule-guided genetic algorithm (RG-GA) for analog circuit optimization. Different from the random mutation approach in the traditional genetic algorithm (GA), the RG-GA introduces a design rule-guided mutation (RGM) mechanism which helps to find the solution region in a more straightforward fashion. Instead of handing over circuit optimization tasks to pure mathematical algorithms, the proposed method takes advantages of valuable design knowledge to improve searching efficiency. This novel algorithm is implemented and deployed to design a two-stage rail-to-rail operational amplifier (OPA), an LC voltage controlled oscillator (LC-VCO) and a four-stage OPA. Experimental results show that compared to the traditional GA method, the RG-GA achieves about 1.5 and 3.3 times speed enhancement for the two-stage rail-to-rail OPA and the LC-VCO, respectively. For the four-stage OPA, the RG-GA method can find an acceptable point within the given number of iterations while the traditional GA could not.
