Embedded memories occupy up to 70% of the die area in modern digital SoCs. Therefore, high-density, low-leakage SRAM cells are desirable. We propose an asymmetrical 4TA SRAM cell and design it and ...conventional 6T, 5T, and 4T SRAM cells under iso-stable constraints. We show that the proposed 4TA cell is denser by up to 16% and has about 10X lower leakage than the iso-stable conventional 4T cell.
In this article, we present a 4.13-GHz ultrahigh-speed (UHS) pseudo two-port SRAM for high-performance computing (HPC) in 4-nm FinFET technology. By applying the bitline (BL) charge time reduction ...(BLCTR) with clamped BL discharge (CBLD) scheme that improves BL charge and write time, the flying word-line (WL) architecture that enhances WL enable time, and the dual address pumping (DAP) architecture with flip-flop that reduces read and write switching time and address latching time, the proposed pseudo two-port SRAM demonstrates a UHS performance with a 4.13-GHz operating speed. A test-chip using the proposed scheme and architecture is fabricated in Samsung 4 nm FinFET technology and demonstrates UHS pseudo two-port 32-Kb SRAM operating at 4.13 GHz under 0.85 V and 100 c conditions.
In this paper, a comparison has been drawn between 5 transistor (5T), 6T and 7T SRAM cells. All the cells have been designed using both single-threshold (conventional) and dual-threshold (dual-Vt) ...voltage techniques. Their respective delays and power consumption have been calculated at 180 nm and 65 nm CMOS technology. With technology scaling, power consumption decreases by 80% to 90%, with some increase in write time because of the utilization of high- Vt transistors in write critical path. The results show that the read delay of 7T SRAM cell is 9% lesser than 5T SRAM cell and 29% lesser than 6T SRAM cell due to the lower resistance of the read access delay path. While read power of 5T SRAM cell is reduced by 10% and 24% as compared to 7T SRAM, 6T SRAM cell respectively. The write speed, however, is degraded by 1% to 3% with the 7T and 5T SRAM cells as compared to the 6T SRAM cells due to the utilization of single ended architecture. While write power of 5T SRAM cell is reduced by up to 40% and 67% as compared to 7T SRAM, 6T SRAM cell respectively.
An offset-compensated cross-coupled PFET bit-line (BL) conditioning circuit (OC-CPBC) and a selective negative BL write-assist circuit (SNBL-WA) are proposed for high-density FinFET static RAM ...(SRAM). The word-line (WL) underdrive read-assist and the negative BL write-assist circuits should be used for the stable operation of high-density FinFET SRAM. However, the WL underdrive read-assist circuit degrades the performance, and the negative BL write-assist circuit consumes a large amount of energy. The OC-CPBC enhances BL development during the evaluation phase by applying cross-coupled PFETs whose offset is compensated by precharging each of the two BLs separately through diode-connected cross-coupled PFETs. The SNBL-WA performs a write assist only when a write failure is detected, and this selective write assist reduces the write energy consumption. The simulation results show that the performance and energy consumption are improved by 41% and 48%, respectively, by applying the OC-CPBC and SNBL-WA to SRAM, even with a decrease in area.
Conventional content addressable memory (BCAM and TCAM) uses specialized 10T/16T bit cells that are significantly larger than 6T SRAM cells. A new BCAM/TCAM is proposed that can operate with standard ...push-rule 6T SRAM cells, reducing array area by 2-5× and allowing reconfiguration of the SRAM as a CAM. In this way, chip area and overall capacitance can be reduced, leading to higher energy efficiency for search operations. In addition, the configurable memory can perform bit-wise logical operations: "AND" and "NOR" on two or more words stored within the array. Thus, the configurable memory with CAM and logical function capability can be used to off-load specific computational operations to the memory, improving system performance and efficiency. Using a 6T 28 nm FDSOI SRAM bit cell, the 64×64 (4 kb) BCAM achieves 370 MHz at 1 V and consumes 0.6 fJ/search/bit. A logical operation between two 64 bit words achieves 787 MHz at 1 V.
This paper describes the use of physical unclonable functions (PUFs) in low-cost authentication and key generation applications. First, it motivates the use of PUFs versus conventional secure ...nonvolatile memories and defines the two primary PUF types: "strong PUFs" and "weak PUFs." It describes strong PUF implementations and their use for low-cost authentication. After this description, the paper covers both attacks and protocols to address errors. Next, the paper covers weak PUF implementations and their use in key generation applications. It covers error-correction schemes such as pattern matching and index-based coding. Finally, this paper reviews several emerging concepts in PUF technologies such as public model PUFs and new PUF implementation technologies.
Under radiation environment, conventional SRAMs suffer from high soft-error rate. To address this challenge, several radiation-hardened static-random access-memory (SRAM) cells such as ...twelve-transistor (12T) Dice and ten-transistor (10T) Quatro have been developed. Quatro is more promising since this cell delivers robust operation while incurring moderate area overhead. However, our study shows that Quatro experiences large number of write failures under parametric variations of scaled technologies, impeding the application of this SRAM cell. In this paper, we present a 12T SRAM cell named as we-Quatro. In spite of using more transistors, the proposed SRAM cell occupies essentially the same area as Quatro. Our extensive simulations show that the proposed cell provides good writability and comparable soft-error resilience to Quatro under parametric variations of 28-nm fully depleted SOI technology, validating the efficacy of our proposed we-Quatro.
Power gating is commonly used to reduce leakage current in SRAM memories; leakage current has a large impact on SRAM energy consumption. We first focus on power gating FinFET SRAMs and then evaluate ...three techniques to reduce the leakage power and energy-delay product (EDP) of sixand eight-transistor (6T, 8T) FinFET SRAM cells. We compare the EDP savings obtained using: 1) power gating FinFETs; 2) near-threshold operation at V DD = 0.6 V instead of the nominal VDD = 1 V; and 3) alternative SRAM cells with shorted gate (SG) and low power (LP) configured FinFETs; LP configuration reverse-biases a FinFET's back gate and reduces leakage current by up to 97%. SRAM cells with higher leakage benefit the most from power gating since they see the largest reductions in leakage current. Sharing power gating transistors among multiple SRAM cells can lead to more leakage current savings, but causes slower read and write speeds which can diminish their effectiveness. Alternative SRAM cells with lower leakage benefit the most from near-threshold operation to further reduce leakage current. Near-threshold operation and/or power gating reduces the 6T SG FinFET SRAM scheme's EDP slightly more than using the 8T SG FinFET SRAM scheme, but using an LP 8T SRAM scheme, such as LP_INV1.2, with near-threshold operation is more effective than power gating and provides the largest reductions in EDP. The design techniques recommended by this brief can enable longer battery life for small sensor systems and thus greater reliability for Internet-of-Things (IoT) devices.
'In-memory computing' is being widely explored as a novel computing paradigm to mitigate the well known memory bottleneck. This emerging paradigm aims at embedding some aspects of computations inside ...the memory array, thereby avoiding frequent and expensive movement of data between the compute unit and the storage memory. In-memory computing with respect to Silicon memories has been widely explored on various memory bit-cells. Embedding computation inside the 6 transistor (6T) SRAM array is of special interest since it is the most widely used on-chip memory. In this paper, we present a novel in-memory multiplication followed by accumulation operation capable of performing parallel dot products within 6T SRAM without any changes to the standard bitcell. We, further, study the effect of circuit non-idealities and process variations on the accuracy of the LeNet-5 and VGG neural network architectures against the MNIST and CIFAR-10 datasets, respectively. The proposed in-memory dot-product mechanism achieves 88.8% and 99% accuracy for the CIFAR-10 and MNIST, respectively. Compared to the standard von Neumann system, the proposed system is <inline-formula> <tex-math notation="LaTeX">6.24\times </tex-math></inline-formula> better in energy consumption and <inline-formula> <tex-math notation="LaTeX">9.42\times </tex-math></inline-formula> better in delay.
Higher variation resilience, lower power consumption, and higher reliability are the three principal design metrics for designing a static random-access memory (SRAM) cell. The most intuitive way to ...achieve lower power consumption is voltage scaling. However, voltage scaling at nanometre technology nodes leads to degradation in the robustness of the SRAM cell and decreased data stability. It is proved that conventional 6T SRAM fails to maintain its stability in scaled technology, particularly in the deep-subthreshold regime. Furthermore, SRAM cells utilising techniques such as read decoupling, for achieving reliable read operation, tend to increase leakage current resulting in higher hold power, which contributes a major portion to the total power consumption in modern internet of things devices. To cater to the requirements of higher robustness and lower hold power dissipation, a transmission gate-based 9T SRAM is proposed, which achieves these requirements at the cost of slightly higher read and write access time. The simulations are performed utilising a 16-nm complementary metal oxide semiconductor model.
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