Exploring the dynamics of photoexcited electrons and holes in green I–III–VI ternary quantum dots (QDs) is of utmost necessity to design and improve their functionality and applicability in devices. ...Here, we have studied the dynamics of photoexcited nascent carriers in CuInS2/ZnS (CISZ) core–shell QDs as potential excited state electron donors using picosecond time-resolved emission and femtosecond transient absorption (fsTA) spectroscopy techniques. The emission decay measurements conducted in the 460–660 nm wavelength range allowed us to distinguish between emission due to electron–hole recombination at conduction (CB) and valence bands (VB), respectively, and due to recombination of the CB electrons and holes at the self-trapped states (Cu1+ centers). The excited state electron transfer (ET) was studied by attaching an anthraquinone-2-carboxylic acid (AQ) electron acceptor to the QDs. The ET from the CB of CISZ QD to AQ was confirmed by the fsTA studies, which revealed the formation of a characteristic anion (AQ–) band at 600 nm. The ET time constant was estimated to be 1.5 ps in ideal one-to-one CISZ-AQ complex, and the charge recombination takes place with time constant >5 ns at delay times beyond the fsTA Instruments reach. We propose that such a long lifetime of the charge-separated state is achieved after hole localization at the (Cu1+) defect, which effectively decouples the hole at the QD and the electron at AQ.
Researchers from Cambridge University's Microelectronics Research Centre and Hitachi Cambridge Laboratory made progress on building a single-electron memory in CMOS. The group has put together a 3 x ...3 memory array based on nanometre-scale Coulomb blockade (CB) memory devices. The team used these to create lateral single-electron memory (L- SEM) cells containing MTJs formed using a heavily doped 50nm silicon nanowire integrated into the memory node on a split-gate MOSFET. The two gates on either side of the central memory node act as switch transistors to connect the memory node to the data line, allowing particular rows in the memory array to be selected by applying a read word line voltage (VRWL) without disturbing the stored data.
