Ternary content-addressable memory (TCAM) is a popular hardware device for fast routing lookup and an attractive solution for applications such as packet forwarding and classification. However, the high cost and power consumption are limiting its popularity and versatility. In this paper, a low leakage power TCAM architecture which uses two-side self power gating technique is proposed to reduce the leakage power dissipation of the mask SRAM cells. The TCAM mask cells are divided into several segments, and the mask bits of one segment are the same except for the boundary segment. In this design, the boundary segment is activated and the others are disabled so that the leakage power can be reduced. The experimental results show that average 26% leakage power can be reduced by using UMC 90 nm CMOS process with 1.0 V supply voltage when compared with the traditional TCAM architecture.