In this paper, a Bayesian optimization approach is proposed for yield optimization of analog and SRAM circuits. Gaussian process (GP) regression is employed to predict the yield over the design space with uncertainty information. An expected improvement acquisition function is constructed over the model and guides the optimization with a utility-based strategy. These techniques, as a whole, can significantly reduce the number of expensive yield estimations during the optimization procedure. Furthermore, the GP model encodes the observation uncertainties of noise-corrupted objectives, which enables an adaptive control over yield estimations. By ensuring high estimation accuracies for promising designs while tolerating higher variabilities for low-yield ones, the proposed method can significantly cut down the average computational cost of yield estimations without surrendering the accuracy of the final result. Experimental results show that, compared with the state-of-the-art yield optimization approaches, the proposed method can significantly reduce the number of circuit simulations without compromising optimization efficacy.