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Keng-Hao Yang; Hsiang-Jen Tsai; Chia-Yin Li; Jendra, Paul; Meng-Fan Chang; Tien-Fu Chen
IEEE transactions on circuits and systems. I, Regular papers, 04/2017, Letnik: 64, Številka: 4Journal Article
As 2.5D/3D die stacking technology emerges, stacked dynamic random access memory (DRAM) has been proposed as a cache due to its large capacity in order to bridge the latency gap between off-chip memory and SRAM caches. The main problems in utilizing a DRAM cache are the high tag storage overhead and the high lookup latency. To address these, we propose tags-in-eDRAM (embedded DRAM) due to its higher density and lower latency. This paper presents an eTag DRAM cache architecture that is composed of a novel tag-comparison-in-memory scheme to achieve direct data access. It eliminates access latency and comparison power by pushing tag-comparison into the sense amplifier. Furthermore, we propose a Merged Tag to enhance the eTag DRAM cache by comparing last-level cache tags and DRAM cache tags in parallel. Simulation results show that the eTag DRAM cache improves energy efficiency by 15.4% and 33.9% in 4-core and 8-core workloads, respectively. Additionally, the Merged Tag achieves 32.1% and 48.7% energy efficiency improvements in 4-core and 8-core workloads, respectively.
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JCR | SNIP | JCR | SNIP | JCR | SNIP | JCR | SNIP |
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Vir: Osebne bibliografije
in: SICRIS
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