This article presents a low-complexity digital low-dropout regulator (DLDO) design featuring a novel voltage regulation and transient enhancement scheme, and a charge-redistribution-based ripple suppression (CRRS) technique that smooths output by redistribution of excessive energy via a small capacitor. Also proposed is a fast-turnaround general DLDO design approach comprising a hybrid discrete-continuous DLDO model and techniques for modeling nonlinear performance enhancement techniques, with which a DLDO's performances for given specifications can be evaluated in the early design stage to shorten the development time. A DLDO test chip fabricated using 110 nm CMOS technology shows a fast settling time of 67 and 250 ns for light-to-heavy (i.e., 2.5 and 50 mA) and heavy-to-light transient, and an output voltage ripple as low as 3 mV with proposed CRRS. The core occupies only 0.022 mm 2 , thanks to the resource-sharing architecture of a proposed digital controller and hardware simplicity. With an input voltage of 1 V and output voltage of 0.85 V, proposed design achieves a peak current efficiency of 99.6% with a 100 MHz operating clock frequency.