High-capacity wireless links at millimeter-Waves are candidate for backhaul infrastructure to small-cell mobile networks. However, the use of high-order modulation schemes sets challenging phase-noise specifications for integrated frequency synthesizers. Moreover, the use of adaptive modulation suggests local oscillators exploiting noise scaling, up to several decibel depending on channel conditions. In this paper, multi-core switch-coupled LC voltage-controlled oscillators are proposed to achieve ultra-low phase noise and scalable noise performance according to system requirements in a power-efficient way. A theoretical model investigating the effect of LC core component mismatches shows very good agreement with experiments. Design insights are provided, key in order to take effective advantage from the proposed low-noise technique. A quad-core ~20 GHz oscillator prototype, followed by a frequency quadrupler, has been realized in 55-nm BiCMOS technology. Measured performances are ~70-to-81 GHz frequency range with -106.5-dBc/Hz minimum phase noise at 1-MHz offset from an 80-GHz carrier with 50-mW power consumption and 1.2-V supply. To authors' knowledge, this is the lowest phase noise measured in the E-Band using integrated technologies and CMOS-compatible supplies. When noise requirements are relaxed, auxiliary cores are turned off rising phase noise by 6 dB but with power consumption reduced down to 18 mW only.