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Aalbers, J; Akerib, D S; Al Musalhi, A K; Amarasinghe, C S; Angelides, N; Araújo, H M; Armstrong, J E; Baker, A; Balashov, S; Bang, J; Bhatti, A; Biekert, A; Brew, C A J; Buuck, M; Chawla, A; Chen, H; Chin, Y T; Chott, N I; Converse, M V; Dahl, C E; David, A; de Viveiros, L; L Di Felice; Ding, C; Eriksen, S R; Fearon, N M; Gaitskell, R J; Genovesi, J; Green, J; M G D van der Grinten; Hall, C R; Han, S; Hartigan-O'Connor, E; Hertel, S A; Heuermann, G; Horn, M; Huang, D Q; Hunt, D; Jacquet, E; Johnson, J; Kannichankandy, M; Khaitan, D; Khazov, A; Kim, J; Kim, Y D; Kingston, J; Kodroff, D; Korolkova, E V; Kraus, H; Kreczko, L; Kudryavtsev, V A; Leonard, D S; Lindote, A; C Lu; Majewski, P A; Maupin, C; McLaughlin, J; Monte, A; Moongweluwan, M; Morales Mendoza, J D; Mount, B J; Murdy, M; Murphy, A St J; Olcina, I; Oliver-Mallory, K C; Orpwood, J; Palladino, K J; Patton, S J; Perry, E; Qie, Y; Rushton, T; Santone, D; Sarkis, R; A B M R Sazzad; Shutt, T; Silk, J J; Silva, C; Sinev, G; Stancu, I; Suerfu, B; Sumner, T J; Tiedt, D R; Timalsina, M; Tong, Z; Tovey, D R; Tranter, J; Trask, M; Tripathi, M; Tronstad, D R; Velan, V; Wang, J J; Wang, Y; Watson, J R; Weeldreyer, L; Wolfs, J D; Woodford, S; Woodward, D; Wright, C J; Xiang, X; Yin, J
arXiv.org, 07/2024Paper, Journal Article
The Data Acquisition System (DAQ) for the LUX-ZEPLIN (LZ) dark matter detector is described. The signals from 745 PMTs, distributed across three subsystems, are sampled with 100-MHz 32-channel digitizers (DDC-32s). A basic waveform analysis is carried out on the on-board Field Programmable Gate Arrays (FPGAs) to extract information about the observed scintillation and electroluminescence signals. This information is used to determine if the digitized waveforms should be preserved for offline analysis. The system is designed around the Kintex-7 FPGA. In addition to digitizing the PMT signals and providing basic event selection in real time, the flexibility provided by the use of FPGAs allows us to monitor the performance of the detector and the DAQ in parallel to normal data acquisition. The hardware and software/firmware of this FPGA-based Architecture for Data acquisition and Realtime monitoring (FADR) are discussed and performance measurements are described.
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