This paper proposes a methodology for extracting the thermal equivalent circuit of a high density GaN-based power stage, using a 48 V to 12 V GaN-based synchronous buck converter as the test platform. The test setup calculates the junction temperatures by measuring R ds, on for both FETs in the half bridge, while current sources produce power losses in each device and the output filter inductor. Independent control of the two gate voltages allows for either symmetric or asymmetric distribution of power loss between the two FETs, and comparison of these results are used to calculate the coupled and uncoupled thermal resistances between them. The thermal interaction with the filter inductor is similarly modeled. The baseline thermal design with a bare PCB and no heatsink was characterized, as well as a proposed thermal solution consisting of a heatsink, gap pad, gap filler, and a plastic shim. Each configuration was tested with three air flow conditions, and the resulting thermal model was used to estimate the maximum current capability without exceeding 100 °C on either FET. The proposed thermal solution improves the maximum current-handling capability by over 60% compared with the baseline design.