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  • CMOS die area temperature c...
    Gorji Zadeh, S. A.; Allidina, Karim; Cicek, Paul-Vahe; Nabki, Frederic; El-Gamal, M. N.

    Analog integrated circuits and signal processing, 12/2022, Letnik: 113, Številka: 3
    Journal Article

    A technique to create a temperature insensitive area on a die using an integrated micro-heater and a phase-locked loop (PLL) configuration is described. The proposed PLL configuration employs thermal feedback through the micro-heater to significantly improve the temperature stability of the die area. Two oscillators employed in the PLL act as temperature sensors to detect the ambient temperature variations and command the thermal loop to compensate it. The temperature stability of these oscillators located in the temperature-compensated die area is improved significantly and can provide a stable timing signal needed for the system. Design methodologies and system-level analysis are presented, and a test-chip for proof-of-concept is designed and fabricated using a standard 130 nm CMOS technology. Analysis and experimental results show that micro-heating provides a low pass filtering effect such that the loop filter and charge pump can be eliminated from the PLL system. Test characterization of the realized proof-of-concept chip shows that the temperature stability of the die area can be improved by a factor as large as 50 × for an ambient temperature range of 36–52 °C. It is shown by simulation that this range can be improved by many folds using SOI CMOS instead of bulk CMOS.