As the most feasible alternative to FinFETs, gate-all-around (GAA) multi-stacked nanosheets known as multi bridge channel FETs were recently introduced. To enjoy improved short channel control with high mobility and GAA characteristics, two critical processing challenges on channels should be overcome: the epitaxial growth of silicon/silicon germanium (Si/SiGe) multi stacks and the clean removal of SiGe. Si surface engineering after SiGe removal is a particularly crucial process. Various methods for removing the sacrificial SiGe layer to form nanosheets were tested in this Letter. Through the measurement of Dit and a flat band voltage (Vfb) shift, a remaining sacrificial SiGe layer was detected. After clean removal of the sacrificial SiGe layer and post cleaning, a Dit of 5 × 1011 cm−2 was achieved, which was similar to that achieved without the removal of SiGe.